ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Clock and Reset Timing
and
describe clock and reset operations. Per
combinations of
CLKIN and clock multipliers/divisors must not result in core/
Table 21. Clock and Reset Timing
Parameter
Timing Requirements
t
CKIN
CLKIN Period
1, 2, 3, 4
t
CKINL
CLKIN Low Pulse
CLKIN High Pulse
t
CKINH
t
WRST
RESET Asserted Pulse Width Low
5
t
NOBOOT
RESET Deassertion to First External Access Delay
6
1
2
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Min
25.0
10.0
10.0
11
t
CKIN
3
t
CKIN
Max
100.0
Unit
ns
ns
ns
ns
ns
5
t
CKIN
Applies to PLL bypass mode and PLL non bypass mode.
CLKIN frequency must not change on the fly.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in
through
Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4
If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN
period is 50 ns.
5
Applies after power-up sequence is complete. See
and
for power-up reset timing.
6
Applies when processor is configured in No Boot Mode (BMODE1-0 = b#00).
t
CKIN
CLKIN
t
CKINL
RESET
t
CKINH
t
WRST
t
NOBOOT
Figure 11. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter
Timing Requirements
t
RST_IN_PWR
RESET Deasserted After the V
DDINT
, V
DDEXT
, V
DDRTC
, and CLKIN Pins Are Stable and 3500
t
CKIN
Within Specification
t
RST_IN_PWR
RESET
Min
Max
Unit
ns
CLKIN
V
DD_SUPPLIES
In
V
DD_SUPPLIES
is V
DDINT
, V
DDEXT
, V
DDRTC
Figure 12. Power-Up Reset Timing
Rev. H
| Page 28 of 64 | January 2011
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