ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing
V
DDEXT
= 1.8 V
Min
Max
4.0
1.0
6.0
1.0
6.0
1.0
0.8
1.0
6.0
V
DDEXT
= 2.5 V/3.3 V
Min
Max
Unit
4.0
0.0
6.0
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT
t
HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT
t
ENDAT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
1
t
DO
t
HO
Output Hold After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
CLKOUT
PROGRAMMED ACCESS
WRITE ACCESS EXTEND HOLD
2 CYCLES
1 CYCLE 1 CYCLE
t
DO
AMSx
t
HO
ABE1–0
ADDR19–1
t
DO
AWE
t
HO
t
SARDY
t
HARDY
ARDY
t
ENDAT
DATA 15–0
t
HARDY
t
SARDY
t
DDAT
Figure 14. Asynchronous Memory Write Cycle Timing
Rev. H
| Page 30 of 64 | January 2011
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