ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing
V
DDEXT
= 1.8 V
Min
Max
2.1
1.0
4.0
1.0
6.0
1.0
0.8
V
DDEXT
= 2.5 V/3.3 V
Min
Max
Unit
2.1
0.8
4.0
0.0
6.0
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT
t
HDAT
DATA15–0 Hold After CLKOUT
t
SARDY
ARDY Setup Before CLKOUT
t
HARDY
ARDY Hold After CLKOUT
Switching Characteristics
Output Delay After CLKOUT
1
t
DO
t
HO
Output Hold After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
SETUP
2 CYCLES
CLKOUT
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
AMSx
t
HO
ABE1–0
ADDR19–1
AOE
t
DO
ARE
t
HO
t
SARDY
ARDY
t
HARDY
t
HARDY
t
SARDY
DATA 15–0
t
SDAT
t
HDAT
Figure 13. Asynchronous Memory Read Cycle Timing
Rev. H
| Page 29 of 64 | January 2011
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