ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
PIN DESCRIPTIONS
ADSP-BF54x Blackfin processors’ pin multiplexing scheme is
listed in Table 11 and the pin definitions are listed in Table 12.
Table 11. Pin Multiplexing
Primary Pin
Function
(Number of
First Peripheral
Function
Second Peripheral
Function
Third Peripheral
Function
Fourth Peripheral
Function
Pins)1, 2
Interrupt Capability
Port A
GPIO (16 pins)
SPORT2 (8 pins)
SPORT3 (8 pins)
TMR4 (1 pin)
TMR5 (1 pin)
TMR6 (1 pin)
TMR7 (1 pin)
TACI7 (1 pin)
TACLK7–0 (8 pins)
Interrupts (16 pins)
Port B
GPIO (15 pins)
TWI1 (2 pins)
UART2 or 3 CTL (2 pins)
UART2 (2 pins)
TACI2-3 (2 pins)
HWAIT (1 pin)
Interrupts (15 pins)
UART3 (2 pins)
SPI2 SEL1-3 (3 pins)
SPI2 (3 pins)
TMR0–2 (3 pins)
TMR3 (1 pin)
Port C
GPIO (16 pins)
SPORT0 (8 pins)
SDH (6 pins)
MXVR MMCLK, MBCLK
(2 pins)
Interrupts (8 pins)3
Interrupts (8 pins)
Port D
GPIO (16 pins)
PPI1 D0–15 (16 pins) Host D0–15 (16 pins) SPORT1 (8 pins)
PPI2 D0–7 (8 pins)
PPI0 D18– 23 (6 pins) Interrupts (8 pins)
Keypad
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Row 0–3
Col 0–3 (8 pins)
Port E
GPIO (16 pins)
SPI0 (7 pins)
Keypad
TACI0 (1 pin)
Row 4–6
Col 4–7 (7 pins)
UART0 TX (1 pin)
Keypad R7 (1 pin)
UART0 RX (1 pin)
UART0 or 1 CTL (2 pins)
PPI1 CLK,FS (3 pins)
TWI0 (2 pins)
Port F
GPIO (16 pins)
PPI0 D0–15 (16 pins) ATAPI D0-15A
Interrupts (8 pins)
Interrupts (8 pins)
Port G
GPIO (16 pins)
PPI0 CLK,FS (3 pins)
DATA 16–17 (2 pins)
TMRCLK (1 pin)
ATAPI A0-2A
Interrupts (8 pins)
Interrupts (8 pins)
SPI1 SEL1–3 (3 pins)
SPI1 (4 pins)
Host CTL (3 pins)
PPI2 CLK,FS (3 pins)
CZM (1 pin)
MXVR MTXON (1 pin) TACI4-5 (2 pins)
CAN0 (2 pins)
CAN1 (2 pins)
Rev. C
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Page 25 of 100
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February 2010
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