ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
through
and
through
describe Serial Port operations.
Table 22. Serial Ports—External Clock
V
DDEXT
= 1.8 V
Min
Max
3.0
3.0
3.0
3.0
8.0
20.0
10.0
0.0
10.0
0.0
0.0
0.0
10.0
V
DDEXT
= 2.5 V/3.3 V
Min
Max
Unit
3.0
3.0
3.0
3.0
4.5
15.0
2
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
t
SDRE
Receive Data Setup Before RSCLKx
1
t
HDRE
Receive Data Hold After RSCLKx
1
t
SCLKEW
TSCLKx/RSCLKx Width
t
SCLKE
TSCLKx/RSCLKx Period
Switching Characteristics
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
3
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
t
DDTE
Transmit Data Delay After TSCLKx
1
t
HDTE
Transmit Data Hold After TSCLKx
1
1
2
Referenced to sample edge.
For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3
Referenced to drive edge.
Table 23. Serial Ports—Internal Clock
V
DDEXT
= 1.8 V V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
LQFP/PBGA MBGA Package
All Packages
Packages
Min
Max
Min
Max
Min
Max
Unit
11.0
−2.0
9.0
0.0
4.5
15.0
3.0
−1.0
3.0
−2.0
6.0
3.0
−2.0
4.5
3.0
−1.0
3.0
9.0
−2.0
9.0
0.0
4.5
15.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0
1
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
−2.0
9.5
t
SDRI
Receive Data Setup Before RSCLKx
1
1
t
HDRI
Receive Data Hold After RSCLKx
0.0
t
SCLKEW
TSCLKx/RSCLKx Width
4.5
t
SCLKE
TSCLKx/RSCLKx Period
20.0
Switching Characteristics
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
−1.0
t
DDTI
Transmit Data Delay After TSCLKx
1
t
HDTI
Transmit Data Hold After TSCLKx
1
−2.5
t
SCLKIW
TSCLKx/RSCLKx Width
6.0
1
2
Referenced to sample edge.
Referenced to drive edge.
Rev. E |
Page 34 of 60 |
July 2007
AD [ ANALOG DEVICES ]
