ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
and
through
describe
parallel peripheral interface operations.
Table 21. Parallel Peripheral Interface Timing
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
Min
Max
8.0
20.0
6.0
1.0
2.0
3.5
1.5
11.0
1.7
11.0
1.8
9.0
1.8
V
DDEXT
= 1.8 V
MBGA Package
Min
Max
8.0
20.0
6.0
1.0
2.0
3.5
1.5
8.0
1.7
9.0
V
DDEXT
= 2.5 V/3.3 V
All Packages
Min
Max
Unit
6.0
15.0
4.0
2
6.0
3
1.0
2.0
3.5
1.5
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
PCLKW
PPI_CLK Width
t
PCLK
PPI_CLK Period
1
t
SFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
t
HFSPE
External Frame Sync Hold After PPI_CLK
t
SDRPE
Receive Data Setup Before PPI_CLK
t
HDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK
1.7
t
DDTPE
Transmit Data Delay After PPI_CLK
t
HDTPE
Transmit Data Hold After PPI_CLK
1.8
1
2
PPI_CLK frequency cannot exceed f
SCLK
/2
Applies when PPI_CONTROL Bit 8 is cleared. See
and
3
Applies when PPI_CONTROL Bit 8 is set. See
and
FRAME
SYNC
IS
DRIVEN
OUT
POLC = 0
PPI_CLK
DATA0
IS
SAMPLED
PPI_CLK
POLC = 1
t
DFSPE
t
POLS = 1
PPI_FS1
POLS = 0
HOFSPE
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. E |
Page 30 of 60 |
July 2007
AD [ ANALOG DEVICES ]
