ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Slave Timing
and
describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
V
DDEXT
= 1.8 V
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
1.6
1.6
10
10
10
10
0
0
0
0
9
9
10
10
V
DDEXT
= 2.5 V/3.3 V
All Packages
Min
Max
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
1.6
1.6
0
0
0
0
8
8
10
10
Parameter
Timing Requirements
t
SPICHS
Serial Clock High Period
2t
SCLK
–1.5
t
SPICLS
Serial Clock Low Period
2t
SCLK
–1.5
t
SPICLK
Serial Clock Period
4t
SCLK
–1.5
2t
SCLK
–1.5
t
HDS
Last SCK Edge to SPISS Not Asserted
t
SPITDS
Sequential Transfer Delay
2t
SCLK
–1.5
t
SDSCI
SPISS Assertion to First SCK Edge
2t
SCLK
–1.5
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup) 1.6
t
HSPID
SCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active
0
t
DSDHI
SPISS Deassertion to Data High Impedance
0
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay)
0
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold) 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISS
(INPUT)
t
SPICHS
SCK
(CPOL = 0)
(INPUT)
t
SPICLS
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
SCK
(CPOL = 1)
(INPUT)
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
HDSPID
t
DDSPID
t
DSDHI
LSB
MISO
(OUTPUT)
CPHA = 1
MOSI
(INPUT)
MSB
t
SSPID
MSB VALID
t
HSPID
t
SSPID
t
HSPID
LSB VALID
t
DSOE
MISO
(OUTPUT)
CPHA = 0
MOSI
(INPUT)
t
DDSPID
MSB
LSB
t
DSDHI
t
HSPID
t
SSPID
MSB VALID
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. E |
Page 38 of 60 |
July 2007
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