ADSP-BF531/ADSP-BF532/ADSP-BF533
FRAME
SYNC
IS
SAMPLED
FOR
DATA0
DATA0 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
DATA1 IS
SAMPLED
t
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
HFSPE
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
t
HFSPE
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
PPI_DATA
t
HDRPE
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (Bit 8 of PPI_CONTROL Set)
Rev. E |
Page 31 of 60 |
July 2007