ADSP-BF531/ADSP-BF532
FRAME
SYNC
IS
SAMPLED
FOR
DATA0
DATA0 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
DATA1 IS
SAMPLED
t
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
HFSPE
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC
IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
t
POLS = 1
PPI_FS1
POLS = 0
SFSPE
HFSPE
DATA0 IS
DRIVEN
OUT
POLS = 1
PPI_FS2
POLS = 0
t
HDTPE
PPI_DATA
DATA0
t
DDTPE
Figure 17. PPI GP Tx Mode with External Frame Sync Timing
Rev. D |
Page 30 of 60 |
August 2006