ADSP-BF531/ADSP-BF532
Parallel Peripheral Interface Timing
and
describe parallel peripheral
interface operations.
Table 20. Parallel Peripheral Interface Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
6.0
15.0
6.0
1.0
3.5
1.5
8.0
1.7
9.0
1.8
1.8
1.7
9.0
6.0
15.0
4.0
1.0
3.5
1.5
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
PCLKW
PPI_CLK Width
t
PCLK
PPI_CLK Period
1
t
SFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
t
HFSPE
External Frame Sync Hold After PPI_CLK
t
SDRPE
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
t
HDRPE
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK
t
DDTPE
Transmit Data Delay After PPI_CLK
t
HDTPE
Transmit Data Hold After PPI_CLK
1
PPI_CLK frequency cannot exceed f
SCLK
/2
FRAME
SYNC
IS
DRIVEN
OUT
POLC = 0
PPI_CLK
DATA0
IS
SAMPLED
PPI_CLK
POLC = 1
t
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
DFSPE
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. D |
Page 29 of 60 |
August 2006
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