ADSP-BF531/ADSP-BF532
Serial Ports
through
and
through
describe Serial Port
operations.
Table 21. Serial Ports—External Clock
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
3.0
3.0
3.0
3.0
4.5
15.0
10.0
0.0
10.0
0.0
0.0
0.0
10.0
3.0
3.0
3.0
3.0
4.5
15.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SFSE
TFS/RFS Setup Before TSCLK/RSCLK
1
t
HFSE
TFS/RFS Hold After TSCLK/RSCLK
1
t
SDRE
Receive Data Setup Before RSCLK
1
t
HDRE
Receive Data Hold After RSCLK
1
t
SCLKEW
TSCLK/RSCLK Width
TSCLK/RSCLK Period
t
SCLKE
Switching Characteristics
t
DFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
2
t
HOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
t
DDTE
Transmit Data Delay After TSCLK
1
t
HDTE
Transmit Data Hold After TSCLK
1
1
2
Referenced to sample edge.
Referenced to drive edge.
Table 22. Serial Ports—Internal Clock
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
11.0
−2.0
9.0
0.0
4.5
15.0
3.0
−1.0
3.0
−2.0
4.5
−2.0
4.5
−1.0
3.0
9.0
−2.0
9.0
0.0
4.5
15.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SFSI
TFS/RFS Setup Before TSCLK/RSCLK
1
t
HFSI
TFS/RFS Hold After TSCLK/RSCLK
1
t
SDRI
Receive Data Setup Before RSCLK
1
t
HDRI
Receive Data Hold After RSCLK
1
t
SCLKEW
TSCLK/RSCLK Width
t
SCLKE
TSCLK/RSCLK Period
Switching Characteristics
t
DFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
2
t
HOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
t
DDTI
Transmit Data Delay After TSCLK
1
Transmit Data Hold After TSCLK
1
t
HDTI
t
SCLKIW
TSCLK/RSCLK Width
1
2
Referenced to sample edge.
Referenced to drive edge.
Rev. D |
Page 32 of 60 |
August 2006
AD [ ANALOG DEVICES ]
