ADSP-BF531/ADSP-BF532
Asynchronous Memory Write Cycle Timing
Table 17. Asynchronous Memory Write Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
4.0
1.0
6.0
1.0
6.0
1.0
0.8
1.0
6.0
4.0
0.0
6.0
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT
t
HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT
t
ENDAT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
1
t
DO
t
HO
Output Hold After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
ACCESS
EXTENDED
1 CYCLE
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
HOLD
1 CYCLE
CLKOUT
t
DO
AMSx
t
HO
ABE1–0
ADDR19–1
ABE, ADDRESS
t
DO
AWE
t
HO
t
SARDY
ARDY
t
HARDY
t
ENDAT
DATA15–0
WRITE DATA
t
SARDY
t
DD AT
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. D |
Page 26 of 60 |
August 2006
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