ADSP-2181
P aram eter
Min
Max
Unit
Bus Request/Gr ant
Timing Requirements:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 17
ns
ns
Switching Characteristics:
tSD
CLKOUT High to xMS,
0.25tCK + 10
ns
RD, WR Disable
xMS, RD, WR
Disable to BG Low
BG High to xMS,
RD, WR Enable
tSDB
tSE
0
ns
ns
ns
ns
ns
0
tSEC
tSDBH
tSEH
xMS, RD, WR
Enable to CLKOUT High
xMS, RD, WR
0.25tCK – 4
Disable to BGH Low2
BGH High to xMS,
RD, WR Enable2
0
0
NOT ES
xMS = PMS, DMS, CMS, IOMS, BMS.
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
WR
tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 10. Bus Request–Bus Grant
REV. D
–16–
ADI [ ADI ]
