ADSP-2181
P aram eter
Min
Max
Unit
ID MA Addr ess Latch
Timing Requirements:
tIALP
tIASU
tIAH
tIKA
tIALS
Duration of Address Latch1, 2
10
5
2
0
3
ns
ns
ns
ns
ns
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
IACK Low before Start of Address Latch1
Start of Write or Read after Address Latch End2, 3
NOT ES
1Start of Address Latch = IS Low and IAL High.
2End of Address Latch = IS High or IAL Low.
3Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
IAL
tIALP
IS
tIASU
tIAH
IAD15–0
tIALS
IRD OR
IWR
Figure 14. IDMA Address Latch
REV. D
–20–
ADI [ ADI ]
