ADSP-2181
P aram eter
Min
Max
Unit
Ser ial P or ts
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
50
4
7
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKIN Width
20
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
T FS/RFSOUT Hold after SCLK High
T FS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
T FS (Alt) to DT Enable
T FS (Alt) to DT Valid
0.25tCK
0
0.25tCK + 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
15
15
0
tRD
tSCDH
tT DE
tT DV
tSCDD
tRDV
0
0
14
15
15
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tSCK
tCC
tCC
SCLK
tSCP
tSCP
tSCS
tSCH
DR
TFS
RFS
IN
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
OUT
ALTERNATE
FRAME MODE
tRDV
RFS
OUT
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
tTDE
tTDV
TFS
IN
ALTERNATE
FRAME MODE
tRDV
RFS
IN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 13. Serial Ports
REV. D
–19–
ADI [ ADI ]
