ADM9240
Table X. Register 43h, INT Interrupt Mask Register 1 (P ower-O n D efault = 00h)
Bit
Nam e
R/W
D escription
0
1
2
3
4
5
6
7
+2.5 V
+VCCP1
+3.3 V
+5 V
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Power-On Default = 0.
T emp
Reserved
FAN1
FAN2
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Table XI. Register 44h, INT Mask Register 2 (P ower-O n D efault = 00h)
Bit
Nam e
R/W
D escription
0
1
2
3
4
5
6
7
+12 V
VCCP2
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Power-up default set to Low.
Power-up default set to Low.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Undefined.
Reserved
Reserved
CI
Reserved
Reserved
RESET Enable
Undefined.
A “1” enables the RESET function in the configuration register.
Table XII. Register 45h, Reserved Com patibility (P ower-O n D efault = 00h)
Bit
Nam e
R/W
D escription
0–7
Reserved
Read/Write
Reserved for Compatibility.
Table XIII. Register 46h, Chassis Intrusion Clear (P ower-O n D efault = 00h)
Bit
Nam e
R/W
D escription
0–6
7
Reserved
Chassis Int. Clear
Read/Write
Read/Write
Undefined (Power On Default = 00h)
A “1” outputs a minimum 20 ms active low pulse on the chassis intrusion
pin. T he register bit clears itself after the pulse has been output.
Table XIV. Register 47h, VID 0–3/Fan D ivisor Register (P ower-O n D efault 0101(VID 3–VID 0))
Bit
Nam e
R/W
D escription
0–3
VID
Read
T he VID[3:0] inputs from processor core power supplies to indicate the
operating voltage (e.g., 1.3 V to 3.5 V).
Sets Counter Prescaler for FAN1 Speed Measurement
<5:4> = 00 – Divide by 1
4–5
FAN1 Divisor
Read/Write
<5:4> = 01 – Divide by 2
<5:4> = 10 – Divide by 4
<5:4> = 11 – Divide by 8
6–7
FAN2 Divisor
Read/Write
Sets Counter Prescaler for FAN2 Speed Measurement
<7:6> = 00 – Divide by 1
<7:6> = 01 – Divide by 2
<7:6> = 10 – Divide by 4
<7:6> = 11 – Divide by 8
–20–
REV. 0
ADI [ ADI ]
