ADM9240
Bit 0 of the Configuration Register controls the monitoring loop
of the ADM9240. Setting Bit 0 low stops the monitoring loop
and puts the ADM9240 into a low power mode thereby reduc-
ing power consumption. Serial bus communication is still pos-
sible with any register in the ADM9240 while in low power
mode. Setting Bit 0 high starts the monitoring loop.
T he structure of the NAND tree is shown in Figure 13.
Beginning with A1 and working clockwise around the chip, each
pin can be toggled and a resulting toggle can be observed on
NT EST _OUT /A0.
Allow for a typical propagation delay of 500 ns.
Bit 1 of the Configuration Register enables or disables the INT
Interrupt output. Setting Bit 1 high enables the INT output,
setting Bit 1 low disables the output.
A1
SDA
SCL
FAN1
FAN2
VID0
VID1
VID2
Bit 3 of the Configuration Register is used to clear the INT
interrupt output when set high. T he ADM9240 monitoring
function will stop until Bit 3 is set low. Interrupt Status Register
contents will not be affected.
NTEST_OUT
VID3
VID4
Bit 4 of the Configuration Register is used to initiate a mini-
mum 20 ms RESET signal on the RESET output if the function
is enabled by Bit 7 in Register 44.
Figure 13. NAND Tree
Note: If any of the inputs shown in Figure 9 are unused, they
should not be connected directly to ground, but via a resistor
such as 10 kΩ. T his will allow the AT E (Automatic T est Equip-
ment) to drive every input high so that the NAND tree test can
be properly carried out.
Bit 6 of the Configuration Register is used to reset the Chassis
Intrusion (CI) output pin when set high.
Bit 7 of the Configuration Register is used to start a Configura-
tion Register Initialization when taken high.
USING TH E AD M9240
P O WER-O N RESET
STARTING CO NVERSIO N
T he monitoring function (analog inputs, temperature and fan
speeds) in the ADM9240 is started by writing to the Configura-
tion Register and setting Start (Bit 0), high, INT_Enable (Bit 1)
high and INT_Clear (Bit 3) low. Apart from initially starting
together, the analog measurements and fan speed measurements
proceed independently and are not synchronized in any way.
When power is first applied, the ADM9240 performs a “power-
on reset” on several of its registers. Registers whose power-on
values are not shown have power-on conditions that are indeter-
minate (this includes the Value and Limit Registers). T he ADC
is inactive. In most applications, usually the first action after
power-on would be to write limits into the Limit Registers.
T he analog measurements will be completed in no more than
353 µs. T he time taken to complete the fan speed measurements
depends on the fan speed and the number of tacho output pulses
per revolution.
Power-on reset clears or initializes the following registers (the
initialized values are shown in T able VI:
– Configuration Register
– Serial Address Register
Once the measurements have been completed, the results can be
read from the Value Registers at any time.
– Interrupt (INT ) Status Registers # 1 and # 2
– Interrupt (INT) Mask Registers # 1 and # 2
– VID /Fan Divisor Register
– VID4 Register
T able IV shows the measurement sequence for the analog inputs.
– Chassis Intrusion Clear Register
– T emperature Configuration Register
– T est Register
Table IV. Measurem ent Sequence
Measurem ent #
P aram eter
– Compatibility Register
– Analog Output Register
1
2
3
4
5
6
7
Analog +VCCP2
Analog +12 VIN
Analog +5 VIN
Analog +3.3 VIN
Analog +2.5 VIN
Analog +VCCP1
T emperature Reading
INITIALIZATIO N
Configuration Register INIT IALIZAT ION performs a similar,
but not identical, function to power-on reset. T he T est Register
and Analog Output Register are not initialized.
Configuration Register INIT IALIZAT ION is accomplished by
setting Bit 7 of the Configuration Register high. T his bit auto-
matically clears after being set.
LO W P O WER AND SH UTD O WN MO D E
T he ADM9240 can be placed in a low power mode by setting
Bit 0 of the Configuration register to 0. T his disables the inter-
nal ADC. Full shutdown mode may then be achieved by setting
Bit 0 of the T est Register to 1. T his turns off the analog output
and stops the monitoring cycle, if running, but it does not affect
the condition of any of the registers. T he device will return to its
previous state when this bit is reset to zero.
Using the Configur ation Register
Control of the ADM9240 is provided through the Configuration
Register. The ADC is stopped upon power-up, and the INT_Clear
signal is asserted, clearing the INT output. T he Configuration
Register is used to start and stop the ADM9240; enable or dis-
able interrupt outputs and modes, and provide the initialization
function described above.
–16–
REV. 0
ADI [ ADI ]
