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ADM9240ARU 参数 Datasheet PDF下载

ADM9240ARU图片预览
型号: ADM9240ARU
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本微处理器系统硬件监控 [Low Cost Microprocessor System Hardware Monitor]
分类和应用: 电源电路电源管理电路微处理器光电二极管监控
文件页数/大小: 22 页 / 283 K
品牌: ADI [ ADI ]
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ADM9240  
INTERRUP T CLEARING  
goes below THOT HYST. Operation in the one-time interrupt  
mode is illustrated in Figure 11. Again, the interval between  
read operations is shown as being longer than the monitoring  
cycle time.  
Reading an Interrupt Status Register will output the contents of  
the Register, then clear it. It will remain cleared until the moni-  
toring cycle updates it, so the next read operation should not be  
performed on the register until this has happened, or the result  
will be invalid. T he time taken for a complete monitoring cycle  
is mainly dependent on the time taken to measure the fan speeds,  
as described earlier.  
T
HOT  
T he INT output is cleared with the INT_Clear bit, which is Bit  
3 of the Configuration Register, without affecting the contents  
of the Interrupt (INT ) Status Registers. When this bit is high,  
the ADM9240 monitoring loop will stop. It will resume when  
the bit is low.  
TEMP  
T
HOTHYST  
INT  
READ  
READ  
READ  
READ  
READ  
READ  
READ  
TEMP ERATURE INTERRUP T MO D ES  
As mentioned earlier, two limit values can be programmed for  
the temperature measurement, a Hot Temperature Limit (THOT),  
and a Hot T emperature Hysteresis Limit (THOT HYST ), which is  
normally some degrees lower.  
Figure 11. INT Output in One-Tim e Interrupt Mode  
CO MP ARATO R MO D E  
Exceeding THOT causes the INT output to go Low. INT will  
remain Low until the temperature goes below THOT. Once the  
temperature goes below THOT, INT will go High. THOT HYST is  
ignored. In other words, Comparator Mode operates like a  
thermostat with no hysteresis. Operation in the comparator  
mode is illustrated in Figure 12.  
T he interrupt function of the temperature sensor differs from  
the interrupt operation of the other inputs in that there are three  
interrupt modes, called “One-T ime Interrupt” mode, “Default  
Interrupt” mode and “Comparator” mode.  
D EFAULT INTERRUP T MO D E  
T
HOT  
Exceeding THOT causes an Interrupt that will remain active  
indefinitely until reset by reading Interrupt Status Register 1 or  
cleared by the INT_Clear bit in the Configuration register.  
Once an Interrupt event has occurred by crossing THOT , then  
reset, an Interrupt will occur again once the next temperature  
conversion has completed. T he interrupts will continue to occur  
TEMP  
INT  
in this manner until the temperature goes below THOT HYST  
.
Operation in the default interrupt mode is illustrated in Figure  
10. For clarity, in this illustration the interval between read  
operations is shown as considerably longer than the monitoring  
cycle time, so that the interrupt is always reasserted after being  
reset, before the next read operation occurs.  
Figure 12. INT Output in Com parator Mode  
RESET INP UT/O UTP UT  
RESET (Pin 12) is an I/O pin that can function as an open-  
drain output, providing a low going 20 ms output pulse when  
Bit 4 of the Configuration Register is set to 1, provided the reset  
function has first been enabled by setting Bit 7 of Interrupt  
Mask Register # 2 to 1. T he bit is automatically cleared when  
the reset pulse is output. Pin 11 can also function as a RESET  
input by pulling this pin low to reset the internal registers of the  
ADM9240 to default values. Only those registers that have  
power on default values as listed in T able VI are affected by this  
function. T he DAC register, Value and Limit Registers are not  
affected.  
T
HOT  
TEMP  
T
HOTHYST  
INT  
READ  
READ  
READ  
READ  
READ  
READ  
READ  
NAND TREE TESTS  
Figure 10. Tem perature INT Output in Default Interrupt  
A NAND tree is provided in the ADM9240 for Automated T est  
Equipment (AT E) board level connectivity testing. T he device  
is placed into NAND T est Mode by powering up with Pin 11  
held high. T his pin is sampled automatically after power-up and  
if it connected high, then the NAND test mode is invoked.  
Mode  
O NE-TIME INTERRUP T MO D E  
Exceeding THOT causes an Interrupt that will remain active  
indefinitely until reset by reading Interrupt Status Register 1 or  
cleared by the INT_Clear bit in the Configuration Register.  
Once an Interrupt event has occurred by crossing THOT , then  
reset, an Interrupt will not occur again until the temperature  
In NAND test mode, all digital inputs may be tested as illus-  
trated below. A0/NT EST _OUT will become the NAND tree  
output pin. T o perform a NAND tree test, all pins included in  
the NAND tree should be driven high.  
REV. 0  
–15–