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ADF4360-3BCPZ 参数 Datasheet PDF下载

ADF4360-3BCPZ图片预览
型号: ADF4360-3BCPZ
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的合成器和VCO [Integrated Synthesizer and VCO]
分类和应用:
文件页数/大小: 24 页 / 317 K
品牌: ADI [ ADI ]
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ADF4360-3  
Data Sheet  
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE  
Experiments have shown that the circuit shown in Figure 22  
provides an excellent match to 50 Ω over the operating range of  
the ADF4360-3. This gives approximately −2 dBm output  
power across the frequency range of the ADF4360-3. Both  
single-ended architectures can be examined using the EV-  
ADF4360-3EB1Z evaluation board.  
The leads on the chip scale package (CP-24) are rectangular.  
The printed circuit board pad for these should be 0.1 mm  
longer than the package lead length and 0.05 mm wider than  
the package lead width. The lead should be centered on the pad  
to ensure that the solder joint size is maximized.  
V
VCO  
The bottom of the chip scale package has a central thermal pad.  
The thermal pad on the printed circuit board should be at least  
as large as this exposed pad. On the printed circuit board, there  
should be a clearance of at least 0.25 mm between the thermal  
pad and the inner edges of the pad pattern to ensure that  
shorting is avoided.  
47nH  
2.7pF  
4.3nH  
RF  
OUT  
50Ω  
Figure 22. Optimum ADF4360-3 Output Stage  
If the user does not need the differential outputs available on  
the ADF4360, the user may either terminate the unused output  
or combine both outputs using a balun. The circuit in Figure 23  
shows how best to combine the outputs.  
Thermal vias may be used on the printed circuit board thermal  
pad to improve thermal performance of the package. If vias are  
used, they should be incorporated in the thermal pad at a  
1.2 mm pitch grid. The via diameter should be between 0.3 mm  
and 0.33 mm, and the via barrel should be plated with 1 ounce  
of copper to plug the via.  
V
VCO  
3.9nH  
1.8pF  
3.9nH  
47nH  
10pF  
2.4nH  
2.4nH  
The user should connect the printed circuit thermal pad to  
AGND. This is internally connected to AGND.  
RF  
RF  
A
B
OUT  
OUT  
50Ω  
OUTPUT MATCHING  
There are a number of ways to match the output of the  
ADF4360-3 for optimum operation; the most basic is to use a  
50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is  
connected in series, as shown Figure 21. Because the resistor is  
not frequency dependent, this provides a good broadband  
match. The output power in this circuit typically gives −3 dBm  
output power into a 50 Ω load.  
1.8pF  
Figure 23. Balun for Combining ADF4360-3 RF Outputs  
The circuit in Figure 23 is a lumped-lattice-type LC balun. It is  
designed for a center frequency of 1.8 GHz and outputs 3.0 dBm  
at this frequency. The series 2.4 nH inductor is used to tune out  
any parasitic capacitance due to the board layout from each  
input, and the remainder of the circuit is used to shift the  
output of one RF input by +90° and the second by −90°, thus  
combining the two. The action of the 3.9 nH inductor and the  
1.8 pF capacitor accomplish this. The 47 nH is used to provide  
an RF choke in order to feed the supply voltage, and the 10 pF  
capacitor provides the necessary dc block. To ensure good RF  
performance, the circuits in Figure 22 and Figure 23 were  
implemented with Coilcraft 0402/0603 inductors and AVX 0402  
thin-film capacitors.  
V
VCO  
51Ω  
100pF  
RF  
OUT  
50Ω  
Figure 21. Simple ADF4360-3 Output Stage  
A better solution is to use a shunt inductor (acting as an RF  
choke) to VVCO. This gives a better match and therefore more  
output power. Additionally, a series inductor is added after the  
dc bypass capacitor to provide a resonant LC circuit. This tunes  
the oscillator output and provides approximately 10 dB  
additional rejection of the second harmonic. The shunt  
inductor needs to be a relatively high value (>40 nH).  
Alternatively, instead of the LC balun shown in Figure 23, both  
outputs may be combined using a 180° rat-race coupler.  
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