Data Sheet
ADF4360-3
ADuC812 Interface
FIXED FREQUENCY LO
Figure 19 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter® Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. When the
third byte has been written, the LE input should be brought
high to complete the transfer.
Figure 18 shows the ADF4360-3 used as a fixed frequency LO at
1.8 GHz. The low-pass filter was designed using ADIsimPLL for
a channel spacing of 8 MHz and an open-loop bandwidth of
40 kHz. The maximum PFD frequency of the ADF4360-3 is
8 MHz. Because using a larger PFD frequency allows users to
use a smaller N, the in-band phase noise is reduced to as low as
possible, –99 dBc/Hz. The 40 kHz bandwidth is chosen to be
just greater than the point at which the open-loop phase noise
of the VCO is –99 dBc/Hz, thus giving the best possible inte-
grated noise. The typical rms phase noise (100 Hz to 100 kHz)
of the LO in this configuration is 0.3°. The reference frequency
is from a 16 MHz TCXO from Fox; thus an R value of 2 is pro-
grammed. Taking into account the high PFD frequency and its
effect on the band select logic, the band select clock divider is
enabled. In this case, a value of 8 is chosen. A very simple pull-
up resistor and dc blocking capacitor complete the RF output
stage.
SCLOCK
MOSI
SCLK
SDATA
ADuC812
I/O PORTS
LE
ADF4360-x
CE
MUXOUT
(LOCK DETECT)
LOCK
DETECT
V
V
VCO
VDD
Figure 19. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are also used to control pow-
erdown (CE input) and detect lock (MUXOUT configured as
lock detect and polled by the port input). When operating in
the described mode, the maximum SCLOCK rate of the
ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 166 kHz.
6
21
DV
2
23
20
10F
V
CE MUXOUT
7
TUNE
CP
AV
DD
V
VCO
DD
14
16
C
N
24
1nF 1nF
FOX
801BE-160
16MHz
REF
IN
22.0nF
3.9nF
51
17 CLK
470
ADF4360-3
18
19
12
DATA
LE
V
VCO
C
C
51
51
100pF
100pF
ADSP-2181 Interface
13
R
SET
1nF
RF
A
B
4
5
OUT
4.7k
CPGND
1
AGND
DGND
RF
Figure 20 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate fram-
ing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
OUT
3
8
9
10 11 22 15
Figure 18. Fixed Frequency LO
INTERFACING
The ADF4360 family has a simple SPI®-compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
will get transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
SCLOCK
SCLK
MOSI
TFS
SDATA
LE
ADF4360-x
ADSP-21xx
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
The maximum allowable serial clock rate is 20 MHz. This
means the maximum update rate possible is 833 kHz or one
update every 1.2 μs. This is certainly more than adequate for
systems that will have typical lock times in hundreds of micro-
seconds.
Figure 20. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
Rev. C | Page 21 of 24
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