ADE7761B
Note that if the on-chip reference is used, actual output
frequencies may vary from device to device due to a reference
tolerance of 8%.
Table 6. f1–4 Frequency Selection
S1
S0
f1–4 (Hz)1
1.72
f1−4 = OSC/2n2
OSC/218
0
0
0
1
3.44
OSC/217
6.13 × 0.66 × 0.66 ×1.72Hz
F , F Frequency =
= 0.367Hz
1
2
1
0
6.86
OSC/216
OSC/21ꢀ
2 × 2 × 2.52
1
1
13.7
CF Frequency = F1, F2 × 64 = 23.5 Hz
1 Values are generated using the nominal frequency of 4ꢀ0 kHz.
2 f1–4 are a binary fraction of the master clock and, therefore, vary with the
internal oscillator frequency (OSC).
As can be seen from these two example calculations, the maximum
output frequency for ac inputs is always half of that for dc input
signals. Table 8 shows a complete listing of all maximum output
frequencies for ac signals.
Frequency Output CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the f1–4
frequency selected, the higher the CF scaling. Table 7 shows
how the two frequencies are related, depending on the states of
Logic Input S0, Logic Input S1, and Logic Input SCF. Because of
its relatively high pulse rate, the frequency at this logic output is
proportional to the instantaneous active power. As with F1 and
F2, the frequency is derived from the output of the low-pass filter
after multiplication. However, because the output frequency is high,
this active power information is accumulated over a much shorter
time. Therefore, less averaging is carried out in the digital-to-
frequency conversion. With much less averaging of the active
power signal, the CF output is much more responsive to power
fluctuations (see Figure 22).
Table 8. Maximum Output Frequencies on CF, F1, and F2 for
AC Inputs
F1, F2 Maximum CF Maximum
Frequency (Hz), Frequency (Hz),
CF-to-F1
Ratio
SCF S1 S0 1/t2
1/t5
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0.37
0.37
0.73
0.73
1.47
1.47
2.94
2.94
46.98
23.49
46.98
23.49
46.98
23.49
46.98
6013
128
64
64
32
32
16
16
2048
FAULT DETECTION
Table 7. Relationship Between CF and F1, F2 Frequency
Outputs
The ADE7761B incorporates a novel fault detection scheme
that warns of fault conditions and allows the ADE7761B to
continue accurate billing during a fault event. The ADE7761B
does this by continuously monitoring both the phase and neutral
(return) currents. A fault is indicated when these currents differ
by more than 6.25%. However, even during a fault, the output
pulse rate on F1 and F2 is generated using the larger of the two
currents. Because the ADE7761B looks for a difference between
the voltage signals on V1A and V1B, it is important that both
current transducers be closely matched.
SCF
S1
S0
f1–4 (Hz)
1.72
1.72
3.44
3.44
6.86
6.86
13.7
13.7
CF Frequency Output
128 × F1, F2
64 × F1, F2
64 × F1, F2
32 × F1, F2
32 × F1, F2
16 × F1, F2
16 × F1, F2
2048 × F1, F2
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
On power-up, the output pulse rate of the ADE7761B is propor-
tional to the product of the voltage signals on V1A and Channel V2.
If the difference between V1A and V1B on power-up is greater than
6.25%, the fault indicator (FAULT) becomes active after about
1 second. In addition, if V1B is greater than V1A, the ADE7761B
selects V1B as the input. Fault detection is automatically disabled
when the voltage signal on Channel V1 is less than 0.3% of the
full-scale input range. This eliminates false detection of a fault
due to noise at light loads.
Example
In this example, if ac voltages of 660 mV peak are applied to
Channel V1 and Channel V2, the expected output frequency on
CF, F1, and F2 is calculated as
Gain = 1, PGA = 0
f1–4 = 1.7 Hz, SCF = S1 = S0 = 0
V1rms = rms of 660 mV peak ac = 0.66/√2 V
V2rms = rms of 660 mV peak ac = 0.66/√2 V
VREF = 2.5 V (nominal reference value)
Rev. 0 | Page 17 of 24
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