ADE7761B
Missing Neutral Gain Calibration
Example
When the ADE7761B is in missing neutral mode, the energy is
billed based on the active current input signal level. The frequency
outputs in this mode can be calibrated with the MISCAL analog
input pin. In this mode, applying a dc voltage of 330 mV on
MISCAL is equivalent to applying, in normal mode, a pure sine
wave on the voltage input with a peak value of 330 mV. The
MISCAL input can vary from 0 V to 660 mV (see the Analog
Inputs section). When set to 0 V, the frequency outputs are
close to zero. When set to 660 mV dc, the frequency outputs are
twice that when MISCAL is at 330 mV dc. In other words,
Equation 7 can be used in missing neutral mode by replacing
V2rms by MISCALrms /√2.
In normal mode, ac voltages of 330 mV peak are applied to
Channel V1 and Channel V2, and then the expected output
frequency on F1 and F2 is calculated as follows:
Gain =1; PGA =0
F1–4 = 1.7 Hz, SCF = S1 = S0 = 0
V1 = rms of 330 mV peak ac = 0.33/√2 V
V2 = rms of 330 mV peak ac = 0.33/√2 V
VREF = 2.5 V (nominal reference value)
6.13× 0.33× 0.33×1.7Hz
F , F2 Frequency =
= 0.0917Hz
1
2 × 2 × 2.52
F , F Frequency =
1
2
CF Frequency = F1, F2 Frequency × 64 = 5.87 Hz
(8)
6.13×Gain×V1rms × MISCALrms / 2 × f1−4
In missing neutral mode, the ac voltage of 330 mV peak is
applied to Channel V1, no signal is connected on Channel V2,
and a 330 mV dc input is applied to MISCAL. With the ADE7761B
in the same configuration as the previous example, the expected
output frequencies on CF, F1, and F2 are
2
VREF
where:
F1, F2 Frequency is the output frequency on F1 and F2 (Hz).
Gain is 1 or 16, depending on the PGA gain selection made
using Logic Input PGA.
6.13× 0.33× 0.33/ 2 ×1.7Hz
F1 , F2 Frequency =
= 0.0917Hz
V1rms is the differential rms voltage signal on Channel V1 (V).
MISCALrms is the differential rms voltage signal on the MISCAL
pin (V).
2 × 2.52
CF Frequency = F1, F2 Frequency × 64 = 5.87 Hz
VREF is the reference voltage (2.5 V 8%) (V).
f1-4 is one of four possible frequencies selected by using Logic
Input S0 and Logic Input S1 (see Table 6).
Rev. 0 | Page 20 of 24
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