AD9865
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V 5ꢀ, DVDD = CLKVDD = DRVDD = 3.3 V 10ꢀ, unless otherwise noted.
Table 7.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
Tx PATH INTERFACE (See Figure 53)
Input Nibble Rate (2× Interpolation)
Input Nibble Rate (4× Interpolation)
Tx Data Setup Time (tDS)
Full
Full
Full
Full
II
II
II
II
20
10
2.5
1.5
160
100
MSPS
MSPS
ns
Tx Data Hold Time (tDH)
ns
Rx PATH INTERFACE1 (See Figure 54)
Output Nibble Rate
Rx Data Valid Time (tDV)
Rx Data Hold Time (tDH)
Full
Full
Full
II
II
II
10
3
0
160
MSPS
ns
ns
1 CLOAD =5 pF for digital data outputs.
EXPLANATION OF TEST LEVELS
I
100% production tested.
II
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
III
IV
V
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. A | Page 8 of 48
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