AD9865
Parameter
Temp
Test Level
Min
Typ
Max
Unit
POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS)2
Tx Mode
IAVDD + ICLKVDD
IDVDD + IDRVDD
Rx Mode
25°C
25°C
IV
IV
112
46
130
49.5
mA
mA
IAVDD + ICLKVDD
IDVDD + IDRVDD
25°C
25°C
IV
IV
225
36.5
253
39
mA
mA
POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (IAVDD + ICLKVDD
)
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
25°C
25°C
25°C
25°C
25°C
25°C
Full
III
III
III
III
III
III
IV
87
108
38
mA
mA
mA
mA
mA
mA
W
10
120
170
107
MAXIMUM ALLOWABLE POWER DISSIPATION
1.66
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
Full
13
mA
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
440
12
20
20
27
ns
ns
ns
ns
ns
CLK PLL and synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
7.8
88
13
20
20
µs
ns
µs
ns
µs
CLK PLL and Synthesizer
1 Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
2 Default power-up settings for MODE = LOW and CONFIG = LOW.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V 5ꢀ, DVDD = CLKVDD = DRVDD = 3.3 V 10ꢀ% RSET = 2 kΩ, unless otherwise noted.
Table 4.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
Full
Full
VI
VI
DRVDD – 0.7
V
V
µA
pF
0.4
12
Full
VI
3
CMOS LOGIC OUTPUTS (CLOAD = 5 pF)
High Level Output Voltage (IOH = 1 mA)
Low Level Output Voltage (IOH = 1 mA)
Output Rise/Fall Time (High Strength Mode and CLOAD = 15 pF)
Output Rise/Fall Time (Low Strength Mode and CLOAD = 15 pF)
Output Rise/Fall Time (High Strength Mode and CLOAD = 5 pF)
Output Rise/Fall Time (Low Strength Mode and CLOAD = 5 pF)
RESET
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
DRVDD – 0.7
V
V
ns
ns
ns
ns
0.4
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
Minimum Low Pulse Width (Relative to fADC
)
1
Clock
cycles
Rev. A | Page 6 of 48
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