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AD9865BCPZ1 参数 Datasheet PDF下载

AD9865BCPZ1图片预览
型号: AD9865BCPZ1
PDF下载: 下载PDF文件 查看货源
内容描述: 宽带调制解调器混合信号前端 [Broadband Modem Mixed-Signal Front End]
分类和应用: 调制解调器
文件页数/大小: 48 页 / 2209 K
品牌: ADI [ ADI ]
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AD9865  
Parameter  
Temp  
Test Level  
Min  
Typ  
Max  
Unit  
Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)  
Latency (Relative to 1/ FDAC  
−0.2 dB Bandwidth  
−3 dB Bandwidth  
Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN  
PLL CLK MULTIPLIER  
)
Full  
Full  
Full  
Full  
V
V
V
V
96  
Cycles  
fOUT/fDAC  
fOUT /fDAC  
dB  
0.1095  
0.1202  
50  
)
OSCIN Frequency Range  
Internal VCO Frequency Range  
Duty Cycle  
Full  
Full  
Full  
IV  
IV  
II  
5
20  
40  
80  
200  
60  
MHz  
MHz  
%
OSCIN Impedance  
CLKOUT1 Jitter5  
25°C  
25°C  
V
III  
100//3  
12  
ΜΩ/pF  
ps rms  
CLKOUT2 Jitter6  
CLKOUT1 and CLKOUT2 Duty Cycle7  
25°C  
Full  
III  
III  
6
ps rms  
%
45  
55  
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).  
2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4x interpolation.  
3 IOUN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation.  
4 Use external amplifier to drive additional load.  
5 Internal VCO operates at 200 MHz , set to divide-by-1.  
6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.  
7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.  
Rx PATH SPECIFICATIONS  
AVDD = 3.3 V 5ꢀ, DVDD = CLKVDD = DRVDD = 3.3 V 10ꢀ% half- or full-duplex operation with CONFIG = 0 default power bias  
settings, unless otherwise noted.  
Table 2.  
Parameter  
Temp  
Test Level  
Min  
Typ  
Max  
Unit  
Rx INPUT CHARACTERISTICS  
Input Voltage Span (RxPGA Gain = −10 dB)  
Input Voltage Span (RxPGA Gain = +48 dB)  
Input Common-Mode Voltage  
Differential Input Impedance  
Full  
Full  
25°C  
25°C  
III  
III  
III  
III  
6.33  
8
1.3  
400  
4.0  
V p-p  
mV p-p  
V
pF  
Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)  
Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz)  
Input Voltage Noise Density (RxPGA Gain = 48 dB, f−3 dBF = 26 MHz)  
RxPGA CHARACTERISTICS  
25°C  
25°C  
25°C  
III  
III  
III  
53  
3.0  
2.4  
MHz  
nV/rtHz  
nV/rtHz  
Minimum Gain  
Maximum Gain  
Gain Step Size  
Gain Step Accuracy  
25°C  
25°C  
25°C  
25°C  
25°C  
III  
III  
III  
III  
III  
−12  
48  
1
Monotonic  
0.5  
dB  
dB  
dB  
dB  
dB  
Gain Range Error  
RxLPF CHARACTERISTICS  
Cutoff Frequency (f−3 dBF ) Range  
Attenuation at 55.2 MHz with f−3 dBF = 21 MHz  
Pass-Band Ripple  
Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS  
Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS  
ADC DC CHARACTERISTICS  
Full  
III  
III  
III  
III  
III  
15  
35  
80  
MHz  
dB  
dB  
ns  
25°C  
25°C  
25°C  
25°C  
20  
1
20  
100  
ns  
Resolution  
Conversion Rate  
NA  
Full  
NA  
II  
10  
Bits  
MSPS  
5
Rev. A | Page 4 of 48  
 
 
 
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