AD9865
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V 5ꢀ, DVDD = CLKVDD = DRVDD = 3.3 V 10ꢀ, unless otherwise noted.
Table 5.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (fSCLK
SCLK Clock High (tHI)
)
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
32
MHz
ns
ns
ns
ns
14
14
14
0
14
0
SCLK Clock Low (tLOW
)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SEN to SCLK Setup Time (tS)
SCLK to SEN Hold Time (tH)
ns
ns
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (fSCLK
SCLK Clock High (tHI)
)
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
32
14
MHz
ns
ns
ns
ns
14
14
14
0
SCLK Clock Low (tLOW
)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SCLK to SDIO (or SDO) Data Valid Time (tDV)
SEN to SDIO Output Valid to Hi-Z (tEZ)
ns
ns
2
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V 5ꢀ, DVDD = CLKVDD = DRVDD = 3.3 V 10ꢀ, unless otherwise noted.
Table 6.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
READ OPERATION1 (See Figure 50)
Output Data Rate
Three-State Output Enable Time (tPZL
Three-State Output Disable Time (tPLZ
Rx Data Valid Time (tVT)
Rx Data Output Delay (tOD)
Full
Full
Full
Full
Full
II
II
II
II
II
5
80
3
3
MSPS
ns
)
)
ns
ns
ns
1.5
4
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (tDS)
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
20
10
5
1
2.5
80
80
50
MSPS
MSPS
MSPS
ns
ns
ns
Tx Data Hold Time (tDH)
Latch Enable Time (tEN)
3
3
Latch Disable Time (tDIS
)
ns
1 CLOAD = 5 pF for digital data outputs.
Rev. A | Page 7 of 48
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