AD9650
Pin No.
Mnemonic
D3−
Type
Description
11
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Output Data 14—True.
Channel A/Channel B LVDS Output Data 14—Complement.
Channel A/Channel B LVDS Output Data 15—True (MSB).
Channel A/Channel B LVDS Output Data 15—Complement (MSB).
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
14
13
16
15
18
17
21
20
23
22
27
26
30
29
32
31
34
33
36
35
39
38
41
40
43
42
25
24
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
D14−
D15+
D15−
OR+
OR−
DCO+
DCO−
SPI Control
45
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44
46
Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
47
48
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. 0 | Page 14 of 44
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