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AD9650BCPZ-65 参数 Datasheet PDF下载

AD9650BCPZ-65图片预览
型号: AD9650BCPZ-65
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 25 MSPS / 65 MSPS / 80 MSPS / 105 MSPS , 1.8 V双通道模拟数字转换器( ADC ) [16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)]
分类和应用: 转换器模数转换器
文件页数/大小: 44 页 / 1640 K
品牌: ADI [ ADI ]
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AD9650  
PIN 1  
INDICATOR  
CLK+  
CLK–  
SYNC  
D0–  
D0+  
D1–  
D1+  
D2–  
D2+  
DRVDD 10  
D3– 11  
D3+ 12  
D4– 13  
D4+ 14  
D5– 15  
D5+ 16  
1
2
3
4
5
6
7
8
9
48 PDWN  
47 OEB  
46 CSB  
45 SCLK/DFS  
44 SDIO/DCS  
43 OR+  
42 OR–  
41 D15+  
40 D15–  
39 D14+  
38 D14–  
37 DRVDD  
36 D13+  
35 D13–  
34 D12+  
33 D12–  
AD9650  
PARALLEL LVDS  
TOP VIEW  
(Not to Scale)  
NOTES  
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE  
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED  
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.  
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)  
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)  
Pin No.  
Mnemonic  
Type  
Description  
ADC Power Supplies  
10, 19, 28, 37  
DRVDD  
AVDD  
Supply  
Supply  
Digital Output Driver Supply (1.8 V Nominal).  
Analog Power Supply (1.8 V Nominal).  
49, 50, 53, 54, 59,  
60, 63, 64  
0
AGND,  
Exposed Pad  
Ground  
The exposed thermal pad on the bottom of the package provides the analog  
ground for the part. This exposed pad must be connected to ground for proper  
operation.  
ADC Analog  
51  
52  
62  
61  
VIN+A  
VIN−A  
VIN+B  
VIN−B  
VREF  
Input  
Input  
Input  
Input  
Differential Analog Input Pin (+) for Channel A.  
Differential Analog Input Pin (−) for Channel A.  
Differential Analog Input Pin (+) for Channel B.  
Differential Analog Input Pin (−) for Channel B.  
55  
Input/output Voltage Reference Input/Output.  
56  
58  
57  
1
SENSE  
RBIAS  
VCM  
CLK+  
CLK−  
Input  
Voltage Reference Mode Select. See Table 11 for details.  
Input/output External Reference Bias Resistor.  
Output  
Input  
Common-Mode Level Bias Output for Analog Inputs.  
ADC Clock Input—True.  
ADC Clock Input—Complement.  
2
Input  
Digital Input  
3
SYNC  
Input  
Digital Synchronization Pin. Slave mode only.  
Digital Outputs  
5
4
7
6
9
8
12  
D0+  
D0−  
D1+  
D1−  
D2+  
D2−  
D3+  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Channel A/Channel B LVDS Output Data 0—True (LSB).  
Channel A/Channel B LVDS Output Data 0—Complement (LSB).  
Channel A/Channel B LVDS Output Data 1—True.  
Channel A/Channel B LVDS Output Data 1—Complement.  
Channel A/Channel B LVDS Output Data 2—True.  
Channel A/Channel B LVDS Output Data 2—Complement.  
Channel A/Channel B LVDS Output Data 3—True.  
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