AD9268
Pin No.
Mnemonic
DꢁA
Type
Description
33
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A Overrange Output.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
34
3ꢀ
36
38
39
4±
41
42
43
4
ꢀ
6
ꢁ
8
9
11
12
13
14
1ꢀ
16
1ꢁ
18
2±
21
22
24
23
D8A
D9A
D1±A
D11A
D12A
D13A
D14A
D1ꢀA (MSB)
ORA
D±B (LSB)
D1B
D2B
D3B
D4B
DꢀB
D6B
DꢁB
D8B
D9B
D1±B
D11B
D12B
D13B
D14B
D1ꢀB (MSB)
ORB
DCOA
DCOB
SPI Control
4ꢀ
44
46
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
4ꢁ
48
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. A | Page 14 of 44
ADI [ ADI ]
