AD9228
6
0 1 7 - 5 7 0 2
AVDD_DUT
CW
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
2 5
1 6
1 5
1 4
1 3
1 2
1 1
1 0
2
2
2
2
1
2
ꢀ k 1 0
R 2 0
3 3
3 1
1
5
3
D
G N
V S
S E R T
GND
ꢀ 0 k 1 0
R 2 0
P N - ꢀ D 1 0 0 k
R 2 6
4
7
9
P N - ꢀ D k 1 0 0
R 2 6 6
ꢀ 0 k 1 0
S 9
8
3
R 2 0
S 1 0
3 2
7
F E V R
6
B – N V I
B _ N V I
B _ N V I
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
D C O
D C O
+
–
D C O
2 4
B + N V I
D D A V
D C O
2 3
2 2
2 1
2 0
T
D _ U D D A V
O
O
F C
O + F C
O – F C
A I S R B
S E N S E
F E V R
B F R E
F C
T U _ D E S E N V S
T U D _ F E V R
C H A
C H A
C H B
C H B
C H C
C H C
A
B
C
D
D +
D – A
1 9
D +
1 8
D – B
1
T
R E F
D D A V
D D A V
3
1 7
T
T
D _ U D D A V
D _ U D D A V
D +
1 6
D – C
1 5
C + N V I
C – N V I
C _ N V I
C _ N V I
C H D
C H D
D +
1 4
D – D
1 3
Figure 73. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
Rev. 0 | Page 39 of 52
ADI [ ADI ]
