AD9200
EXTERNAL REFERENCE OPERATION
4V
2V
VIN
Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9200.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.
REFTS
REFTF
4V
2V
AD9200
10
F
0.1
0.1
F
F
REFBF
0.1
F
REFBS
VREF
The AD9200 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 kΩ load.
REFSENSE
MODE
AVDD
Figure 21 shows an example of the user driving the top and bottom
references. REFTS is connected to a low impedance 2 V source
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as
long as the difference between them is between 1 V and 2 V.
Figure 23a. External Reference—2 V p-p Input Span
REFTS
+5V
C4
0.1
F
6
5
2V
8
AIN
7
AD9200
REFTF
SHA
1V
C3
0.1
REFT
C6
0.1
F
C2
10
AD9200
F
F
0.1F
10k⍀
REFTF
REFBS
10k⍀
10k⍀
REFTS
REFBS
C5
0.1
2V
1V
2
3
F
A2
0.1F
6
A/D
CORE
4.2k⍀
TOTAL
10F
REFBF
REFB
C1
0.1
4
F
REF
SENSE
0.1F
10k⍀
AVDD
MODE
REFBF
Figure 23b. Kelvin Connected Reference Using the AD9200
Figure 21. External Reference Mode—1 V p-p Input Span
STANDBY OPERATION
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 4 mW. If there is no connection to the
STBY pin, an internal pull-down circuit will keep the ADC in a
“wake-up” mode of operation.
Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose
this op amp based on noise and accuracy requirements.
The ADC will “wake up” in 400 ns (typ) after the standby pulse
goes low.
AD9200
3.0V
2.5V
2.0V
AIN
CLAMP OPERATION
AVDD
AVDD
The AD9200ARS and AD9200KST parts feature an optional
clamp circuit for dc restoration of video or ac coupled signals.
Figure 24 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the
clamp, apply a logic high to the CLAMP pin. This will close
the switch SW1. The clamp amplifier will then servo the volt-
age at the AIN pin to be equal to the clamp voltage applied at
the CLAMPIN pin. After the desired clamp level is attained,
SW1 is opened by taking CLAMP back to a logic low. Ignoring
the droop caused by the input bias current, the input capacitor
CIN will hold the dc voltage at AIN constant until the next
clamp interval. The input resistor RIN has a minimum recom-
mended value of 10 Ω, to maintain the closed-loop stability of
the clamp amplifier.
REFTS
REFBS
0.1F
0.1F
0.1F
REFTF
10F
1.5k⍀
A3
0.1F
10F
VREF
MODE
1.0F
0.1F
REFBF
0.1F
1k⍀
+5V
AVDD
REFSENSE
REF43
0.1F
AVDD/2
Figure 22. External Reference Mode—1 V p-p Input
Span 2.5 VCM
Figure 23a shows an example of the external references driving
the REFTF and REFBF pins that is compatible with the
AD876. REFTS is shorted to REFTF and driven by an external
4 V low impedance source. REFBS is shorted to REFBF and
driven by a 2 V source. The MODE pin is connected to GND
in this configuration.
The allowable voltage range that can be applied to CLAMPIN
depends on the operational limits of the internal clamp ampli-
fier. When operating off of 3 volt supplies, the recommended
clamp range is between 0.5 volts and 2.0 volts.
REV. E
–12–
ADI [ ADI ]
