AD9200
The actual reference voltages used by the internal circuitry of
the AD9200 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
AIN
AD9200
MODE
SHA
AVDD
0V
0.1F
REFTF
10k⍀
REFTF
10F
0.1F
AD9200
10k⍀
10k⍀
REFTS
REFBS
REFBF
A2
0.1F
A/D
CORE
4.2k⍀
TOTAL
10F
0.1F
0.1F
0.1F
10k⍀
Figure 17. Reference Decoupling Network
REFBF
VREF
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
A1
1V
1.0F
0.1F
REF
SENSE
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figures 18, 19 and 20 show example hookups of the AD9200
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9200
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0 µF tantalum capacitor in
parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
1V
AIN
AD9200
2V
MODE
AIN
AD9200
SHA
AVDD
MODE
0V
AVDD/2
SHA
1V
0.1F
10k⍀
REFTF
0.1F
REFTF
10k⍀
10k⍀
10k⍀
REFTS
REFBS
10k⍀
10k⍀
REFTS
REFBS
A2
0.1F
A/D
CORE
4.2k⍀
TOTAL
10F
A2
+1.5V
0.1F
A/D
CORE
4.2k⍀
TOTAL
10F
0.1F
10k⍀
0.1F
10k⍀
REFBF
REFBF
VREF
A1
VREF
1V
A1
REF
SENSE
1V
1.0F
0.1F
REF
SENSE
0.1F
1.0F
Figure 18. Internal Reference 1 V p-p Input Span
(Top/Bottom Mode)
Figure 20. Internal Reference 1 V p-p Input Span,
(Center Span Mode)
REV. E
–11–
ADI [ ADI ]
