AD775
In the topology shown in Figure 8, the top of the ladder (VRT
)
NC
16
17
VRTS
VRT
is shorted to the top bias resistor (VRT S) (Pin 17 shorted to Pin
16), while the bottom of the ladder (VRB) is shorted to the bot-
tom bias resistor (VRBS) (Pin 23 shorted to Pin 22). T his creates
a resistive path (nominally 725 ohms) between AVDD and AVSS
For nominal supply voltages (5 V and 0 V respectively), this
creates an input range of 0.64 V to 2.73 V.
10kΩ
10kΩ
+5V
0.1µF
AD680
500pF
AD775
3
VIN
VOUT
2
.
2
3
GND
1
20Ω
422Ω
0.1µF
1
AD822
0.1µF
22
23
NC
VRBS
VRB
10kΩ
Both top and bottom of the reference ladder should be de-
500pF
0.1µF
coupled, preferably with a chip capacitor to ground to minimize
reference noise.
NC = NO CONNECT
422Ω
10kΩ
6
5
20Ω
7
AD822
T he topology shown in Figure 9 provides a ground-inclusive
input range. T he bottom of the ladder (VRB) is shorted to AVSS
(0 V), while the top of the ladder (VRT ) is connected to the on-
.
140Ω
board bias resistor (VRT S). T his provides a nominal input range
of 0 V to +2.4 V for AVDD of 5 V. T he VRBS pin may be left
floating, or shorted to AVSS
.
Figure 11. Reference Configuration: 0.7 V to 3.2 V
ANALO G INP UT
AV
DD
T he impedance looking into the analog input is essentially
capacitive, as shown in the equivalent circuit of Figure 12, typi-
cally totalling around 11 pF. A portion of this capacitance is
parasitic; the remainder is part of the switched capacitor struc-
ture of the comparator arrays. T he switches close on the rising
edge of the clock, acquire the input voltage, and open on the
clock’s falling edge (the sampling instant). T he charge that must
be moved onto the capacitors during acquisition will be a func-
tion of the converter’s previous two samples, but there should be
no sample-to-sample crosstalk so long as ample driving imped-
ance and acquisition time are provided.
325Ω
AD775
16
17
0.1µF
300Ω
*VALUES FOR
RESISTANCE
ARE TYPICAL
23
22
AV
SS
90Ω
AV
SS
SWITCHES EACH
CLOCK CYCLE
Figure 9. Reference Configuration: 0 V to +2.4 V
AV
DD
More elaborate topologies can be used for those wishing to
provide an input span based on an external reference voltage.
T he circuit in Figure 10 uses the AD780 2.5 V reference to
drive the top of the ladder (VRT ), with the bottom (VRB) of the
ladder grounded to provide an input span of 0 V to +2.5 V. This is
modified in Figure 11 to shift the 2.5 V span up 700 mV.
C2
V
IN
SWITCHES ON ALTERNATE
C1
CLOCK CYCLES
C3
+5V
AV
SS
AD780
AD775
1
2
3
4
8
7
6
5
C1 + C2 + C3 ≈ 11pF
NC
NC
NC
NC
16
17
NC
Figure 12. Equivalent Analog Input Circuit (VIN)
0.1µF
0.1µF
NC
AD775
For example, to ensure accurate acquisition (to 1/4 bit accuracy)
of a full-scale input step in less than 20 ns, a source impedance
of less than 100 ohms is recommended. Figure 13 shows one
option of input buffer circuitry using the AD817. T he AD817
acts as both an inverting buffer and level shifting circuit. In
order to level shift the ground-based input signal to the dc level
required by the input of the AD775, the supply voltage is resis-
tively divided to produce the appropriate voltage at the nonin-
verting input of the AD817. For most applications, the AD817
provides a low cost, high performance level shifter. T he AD811
is recommended for systems which require faster settling times.
22
23
NC
NC = NO CONNECT
Figure 10. Reference Configuration: 0 V to 2.5 V
T he AD775 can accommodate dynamic changes in the reference
voltage for gain or offset adjustment. However, conversions that
are in progress, including those in the converter pipeline, while
the reference voltages are changing will be invalid.
REV. 0
–7–
ADI [ ADI ]
