AD775
P O WER SUP P LY CO NNECTIO NS AND D ECO UP LING
T he analog and digital supplies of the AD775 have been sepa-
rate to prevent the typically large transients associated with the
on-chip digital circuitry from coupling into the analog supplies
(AVDD, AVSS). However, in order to avoid possible latch-up
conditions, AVDD and DVDD must share a common supply
external to the part, preferably a common source somewhere on
the PC board.
AP P LICATIO NS
AD 775 EVALUATIO N BO ARD
Figures 17 through 22 show the schematic and printed circuit
board (PCB) layout for the AD775 evaluation board. Referring
to Figure 17, the input signal is buffered by U3, an AD817 op
amp configured as a unity-gain follower. T he signal is then ac-
coupled and dc-biased by adjusting potentiometer R14. Video
and imaging applications would typically use a dc-restoration
circuit instead of the manual potentiometer adjustment. Q1, an
emitter-follower, buffers the input signal and provides ample
current to drive a simple low-pass filter. T he filtering is included
to limit wideband noise and highlight the fact that the AD775
can be driven from a nonzero source impedance.
Each supply should be decoupled by a 0.1 µF capacitor located
as close to the device pin as possible. Surface-mount capacitors,
by virtue of their low parasitic inductance, are preferable to
through-hole types. A larger capacitor (10 µF electrolytic)
should be located somewhere on the board to help decouple
large, low frequency supply noise. For specific layout informa-
tion, refer to the AD775 Evaluation Board section of the data
sheet.
T he reference circuit is similar to the one shown in Figure 11
with the exception that R1 and R2 allow precise adjustment of
J8
+5VA
+5VA
CLOCK
TP10
(
)
R15
5
6
9
8
CR1
1N4148
499
A
R14
500
R16
49.9
1/6
U7
TP9
1/6
U7
V
CC
D
U3
R13
20
TP5
IN
J1
ANALOG
INPUT
2
3
V
TP2
R4
Q1
6
AD817
4
2N3904
7
C8
22µF
TP1
R11
75
TP13
C7
10pF
49.9
+5VA
+5V
R12
4.99k
ENABLE
C6
C5
EE
P2-40 PIN IDC
1
A
C15
D
C18
A
A
V
V
V
EE
CC
+5V
D
AD775
74ALS541
C22
D
D
13
DV
CLK 12
DD
DD
DD
1
2
3
20
19
18
17
16
15
14
13
12
11
J10
14 AV
15 AV
DV
DD
G1
A1
A2
V
CC
11
10
9
D
TP4
D7
G2
Y1
Y2
Y3
V
RT
R8
10k
R9
10k
16
17
V
V
D6
D5
D4
D3
D2
D1
D0
RTS
J3
J6
4
5
U5
8
A3
A4
A5
A6
A7
A8
RT
U6
C4
390pF
C13
18 AV
7
A
DD
+5VA
3
U1
AD680
6
7
A
19
20
21
22
23
24
6
V
Y4
Y5
IN
1/2 U2
R10
20
C14
2
2
3
AV
AV
V
5
SS
SS
V
V
IN
OUT
8
1
AD822
8
4
Y6
Y7
Y8
GND
C12
9
C9
A
C2
1
A
J4
3
2
1
RBS
RB
J5
D
10
A
GND
V
DV
A
SS
+5VA
R3
499
J2
DV
OE
SS
J9
TP3
D
C1
A
VRB
C3
390pF
R6
10k
R2
D
R7
R5
20
500
10k
1/2 U2
7
6
5
AD822
A
R1
500
4
TP12
TP6
A
+5V
A
J7
NOTES
40
D
= 47µF ELECTROLYTIC CAPACITOR
78M05
U4
C21
V
CC
UNLESS OTHERWISE NOTED
+5VA
D
TP7
V
2
CC
= 0.1µF CERAMIC CAPACITOR
1
3
5
V
V
IN
OUT
UNLESS OTHERWISE NOTED
GND
C16
C11
TP8
4
6
A
C19
C20
TP11
V
EE
V
EE
Figure 17. AD775 Evaluation Board Schem atic
–9–
REV. 0
ADI [ ADI ]
