AD775
D EFINITIO NS O F SP ECIFICATIO NS
D iffer ential P hase
Integr al Nonlinear ity (INL)
T he difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” T he
point used as “zero” occurs 1/2 LSB before the first code tran-
sition. “Full scale” is defined as a level 1 1/2 LSB beyond the
last code transition. T he deviation is measured from the center
of each particular code to the true straight line.
P ipeline D elay (Latency)
T he number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
D iffer ential Nonlinear ity (D NL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) is guaranteed.
Signal-to-Noise P lus D istor tion Ratio (S/N+D )
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components including har-
monics but excluding dc. T he value for S/N+D is expressed in
decibels.
O ffset Er r or
Total H ar m onic D istor tion (TH D )
T he first code transition should occur at a level 1/2 LSB above
nominal negative full scale. Offset referred to the Bottom of
Ladder VRB is defined as the deviation from this ideal. T he last
code transition should occur 1 1/2 LSB below the nominal
positive full scale. Offset referred to the T op of Ladder VRT is
defined as the deviation from this ideal.
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is ex-
pressed as a percentage or in decibels.
D iffer ential Gain
T he percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low fre-
quency signal on which it is superimposed.
TH EO RY O F O P ERATIO N
AP P LYING TH E AD 775
T he AD775 uses a pipelined two-step (subranging) flash archi-
tecture to achieve significantly lower power and lower input
capacitance than conventional full flash converters while still
maintaining high throughput. T he analog input is sampled by
the switched capacitor comparators on the falling edge of the
input clock: no external sample and hold is required. T he coarse
comparators determine the top four bits (MSBs), and select the
appropriate reference ladder taps for the fine comparators. With
the next falling edge of the clock, the fine comparators determine
the bottom four bits (LSBs). Since the LSB comparators require
a full clock cycle between their sampling instant and their deci-
sion, the converter alternates between two sets of fine compara-
tors in a “ping-pong” fashion. T his multiplexing allows a new
input sample to be taken on every falling clock edge, thereby
providing 20 MSPS operation. T he data is accumulated in the
correction logic and output through a three-state output latch
on the rising edge of the clock. T he latency between input sam-
pling and the corresponding converted output is 2.5 clock cycles.
REFERENCE INP UT
T he AD775 features a resistive reference ladder similar to that
found in most conventional flash converters. T he analog input
range of the converter falls between the top (VRT ) and bottom
(VRB) voltages of this ladder. T he nominal resistance of the lad-
der is 300 ohms, though this may vary from 230 ohms to 450
ohms. T he minimum recommended voltage for VRB is 0 V; the
linearity performance of the converter may deteriorate for input
spans (VRB–VRB) below 1.8 V. While 2.8 V is the recommended
maximum ladder top voltage (VRT ), the top of the ladder may be
as high as the positive supply voltage (AVDD) with minimal lin-
earity degradation.
AV
DD
325Ω
AD775
16
17
0.1µF
All three comparator banks utilize the same resistive ladder for
their reference input. T he analog input range is determined by
the voltages applied to the bottom and top of the ladder, and
the AD775 can digitize inputs down to 0 V using a single sup-
ply. On-chip application resistors are provided to allow the
ladder to be conveniently biased by the supply voltage.
300Ω
*VALUES FOR
RESISTANCE
ARE TYPICAL
23
22
T he AD775 uses switched capacitor autozeroing techniques to
cancel the comparators’ offsets and achieve excellent differential
nonlinearity performance: typically ±0.3 LSB. T he integral
nonlinearity is determined by the linearity of the reference lad-
der and is typically +0.5 LSB.
0.1µF
90Ω
AV
SS
Figure 8. Reference Configuration: 0.64 V to 2.73 V
T o simplify biasing of the AD775, on-chip reference bias resis-
tors are provided on Pins 16 and 22. T he two recommended
configurations for these resistors are shown in Figures 8 and 9.
–6–
REV. 0
ADI [ ADI ]
