AD775
1kΩ
100
90
80
70
60
50
40
30
1kΩ
AD775
0VDC
+5V
1.5VDC
AIN
19
AD817
5.6kΩ
10µF
1kΩ
Figure 13. Level Shifting Input Buffer
T he analog input range is set by the voltage at the top and bot-
tom of the reference ladder. In general, the larger the span
(VRT –VRB), the better the differential nonlinearity (DNL) of the
converter; a 1.8 V span is suggested as a minimum to realize
good linearity performance. AS the input voltage exceeds 2.8 V
(for AVDD = 4.75 V), the input circuitry may start to slightly
degrade the acquisition performance.
0
10
20
30
40
CLOCK FREQUENCY – MHz
Figure 15. Power Dissipation vs. Clock Frequency
In applications sensitive to aperture jitter, the clock signal
should have a fall time of less than 3 ns. High speed CMOS
logic families (HC/HCT ) are recommended for their symmetri-
cal swing and fast rise/fall times. Care should be taken to mini-
mize the fanout and capacitive loading of the clock input line.
CLO CK INP UT
T he AD775’s internal control circuitry makes use of both clock
edges to generate on-chip timing signals. T o ensure proper
settling and linearity performance, both tCH and tCL times
should be 25 ns or greater. For sampling frequencies at or near
20 MSPS, a 50% duty cycle clock is recommended. For slower
sampling applications, the AD775 can accommodate a wider
range of duty cycles, provided each clock phase is as least 25 ns.
D IGITAL INP UTS AND O UTP UTS
T he AD775’s digital interface uses standard CMOS, with logic
thresholds roughly midway between the supplies (DVSS, DVDD).
T he digital output is presented in straight binary format, with
full scale (1111 1111) corresponding to VIN = VRT , and zero
(0000 0000) corresponding to VIN = VRB. Excessive capacitive
loading of the digital output lines will increase the dynamic
power dissipation as well as the on-chip digital noise. Logic
fanout and parasitic capacitance on these lines should be mini-
mized for optimum noise performance.
Under certain conditions, the AD775 can be operated at sam-
pling rates above 20 MSPS. Figure 14 shows the signal-to-noise
plus distortion (S/(N+D)) performance of a typical AD775
versus clock frequency. It is extremely important to note that the
maximum clock rate will be a strong function of both temperature and
supply voltage. In general, the part slows down with increasing
temperature and decreasing supply voltage.
T he data output lines may be placed in a high output impedance
state by bringing OE (Pin 1) to a logic high. Figure 16 indicates
typical timing for access and float delay times (tH L and tDD
respectively). Note that even when the outputs are in a high
impedance state, activity on the digital bus can couple back to
the sensitive analog portions of the AD775 and corrupt conver-
sions in progress.
50
40
30
20
10
0
OE
tDD
tHL
DATA
OUTPUT
DATA ACTIVE
THREE-STATE
(HIGH IMPEDANCE)
t
DD = 18ns TYPICAL
tHL = 12ns TYPICAL
0.1
1
10
100
CLOCK FREQUENCY – MHz
Figure 16. High Im pedance Output Tim ing
Figure 14. S(N + D) vs. Clock Frequency (Tem perature
= +25°C)
A significant portion of the AD775’s power dissipation is pro-
portional to the clock frequency: Figure 15 illustrates this
tradeoff for a typical part.
–8–
REV. 0
ADI [ ADI ]
