AD7714
TIMING
Parameter
f
CLKIN3, 4
t
CLK IN LO
t
CLK IN HI
t
DRDY
t
1
t
2
Read Operation
t
3
t
4
t
5 6
t
6
t
7
t
8
t
9 7
t
10
Write Operation
t
11
t
12
t
13
t
14
t
15
t
16
DD
DD
1, 2
Logic 1 = DV unless otherwise noted.)
DD
CHARACTERISTICS
(AV = DV = +2.7 V to +5.25 V; AGND = DGND = 0 V; f
CLKIN
= 2.5 MHz; Input Logic 0 = 0 V,
Limit at T
MIN
, T
MAX
(A, Y Versions)
400
2.5
0.4
×
t
CLK IN
0.4
×
t
CLK IN
500
×
t
CLK IN
100
100
0
0
0
80
100
100
100
0
10
60
100
100
0
30
20
100
100
0
Units
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Master Clock Frequency: Crystal/Resonator or Externally
Supplied
For Specified Performance
Master Clock Input Low Time. t
CLK IN
= 1/f
CLK IN
Master Clock Input High Time
DRDY
High Time
SYNC
Pulsewidth
RESET
Pulsewidth
DRDY
to
CS
Setup Time
CS
Falling Edge to SCLK Active Edge Setup Time
5
SCLK Active Edge to Data Valid Delay
5
DV
DD
= +5 V
DV
DD
= +3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Active Edge Hold Time
5
Bus Relinquish Time after SCLK Active Edge
5
DV
DD
= +5 V
DV
DD
= +3 V
SCLK Active Edge to
DRDY
High
5, 8
CS
Falling Edge to SCLK Active Edge Setup Time
5
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Edge Hold Time
2
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 6 and 7. Timing applies for all grades.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7714 is production tested with f
CLKIN
at 2.4576 MHz (1 MHz for some I
DD
tests). It is guaranteed by characterization to operate at 400 kHz.
5
SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
7
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
8
DRDY
returns high after the first read from the device after an output update. The same data can be read again, if required, while
DRDY
is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
ORDERING GUIDE
Model
I
SINK
(800 A AT DV
DD
= +5V
100 A AT DV
DD
= +3.3V)
AV
DD
Supply
5V
5V
5V
3V
3V
3V
3 V/5 V
3 V/5 V
3 V/5 V
5V
3V
5V
3V
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Evaluation Board
Package
Option*
N-24
R-24
RS-28
N-24
R-24
RS-28
N-24
R-24
RU-24
Die
Die
TO OUTPUT
PIN
50pF
+1.6V
I
SOURCE
(200 A AT DV
DD
= +5V
100 A AT DV
DD
= +3.3V)
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
AD7714AN-5
AD7714AR-5
AD7714ARS-5
AD7714AN-3
AD7714AR-3
AD7714ARS-3
AD7714YN
AD7714YR
AD7714YRU
AD7714AChips-5
AD7714AChips-3
EVAL-AD7714-5EB
EVAL-AD7714-3EB
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
REV. C
–7–
AD [ ANALOG DEVICES ]
