AD7008
Table I. Latency Table
Function
FSelect
Phase
IQ Mod
Latency
(Synchronizer Enabled CR3 = 0
1
)
14t
1
13t
1
11t
1
NOTE
1
All latencies are reduced by 4t
1
when CR3 = 1 (synchronizer disabled). 1t
1
is
equal to one pipeline delay.
Table II. Source and Destination Register
TC3
X
0
1
1
1
1
1
1
1
1
TC2
X
0
0
0
0
0
1
1
1
1
TC1
X
X
0
0
1
1
0
0
1
1
TC0
X
X
0
1
0
1
0
1
0
1
LOAD
0
1
1
1
1
1
1
1
1
1
Source Register
N/A
Parallel
Parallel
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Destination Register
N/A
COMMAND*
FREQ0
FREQ1
PHASE
IQMOD
FREQ0
FREQ1
PHASE
IQMOD
*The Command Register can only be loaded from the parallel assembly registers.
Table III. AD7008 Control Registers
Register
Size
Reset State Description
Command Register. This is written to using the parallel assembly register.
Frequency Register 0. This defines the output frequency, when
FSELECT = 0, as a fraction of the CLOCK frequency.
Frequency Register 1. This defines the output frequency, when
FSELECT = 1, as a fraction of the CLOCK frequency.
Phase Offset Register. The contents of this register is added to the
output of the phase accumulator.
I and Q Amplitude Modulation Register. This defines the amplitude of
the I and Q signals as 10-bit twos complement binary fractions.
DB[19:10] is multiplied by the Quadrature (sine component and
multiplied by the In-Phase (cosine) component.
COMMAND REG* 4 Bits CR3–CR0
All Zeros
FREQ0 REG
32 Bits DB31–DB0 All Zeros
FREQ1 REG
PHASE REG
IQMOD REG
32 Bits DB31–DB0 All Zeros
12 Bits DB11–DB0 All Zeros
20 Bits DB19–DB0 All Zeros
*On power up, the Command Register should be configured by the user for the desired mode before operation.
Table IV. Command Register Bits*
CR0
=0
=1
CR1
CR2
CR3
=0
=1
=0
=1
=0
=1
Eight-Bit Databus. Pins D15–D8 are ignored and the parallel assembly register shifts eight places left on each write.
Hence four successive writes are required to load the 32-bit parallel assembly register, Figure 6.
Sixteen-Bit Databus. The parallel assembly register shifts 16 places left on each write. Hence two successive writes are
required to load the 32-bit parallel assembly register, Figure 5.
Normal Operation.
Low Power Sleep Mode. Internal Clocks and the DAC current sources are turned off.
Amplitude Modulation Bypass. The output of the sine LUT is directly sent to the DAC.
Amplitude Modulation Enable. IQ modulation is enabled allowing AM or QAM to be performed.
Synchronizer Logic Enabled. The FSELECT, LOAD and TC3–TC0 signals are passed through a 4-stage pipeline
to synchronize them with the CLOCK, avoiding metastability problems.
Synchronizer Logic Disabled. The FSELECT, LOAD and TC3–TC0 signals bypass the synchronization logic. This
allows for faster response to the control signals.
*The Command Register can only be loaded from the parallel assembly register.
REV. B
–7–
AD [ ANALOG DEVICES ]
