AD7008
TIMING CHARACTERISTICS
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
AD7008AP20
Min
Typ
Max
50
20
20
5
3
4t
1
2t
1
5
5
10
10
20
10
3
3
20
8
8
10
10
AA
= V
DD
+5 V
±
5%; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
AD7008JP50
Min
Typ
Max
20
8
8
5
3
4t
1
2t
1
5
5
10
10
20
10
3
3
20
8
8
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
CLOCK Period
CLOCK High Duration
CLOCK Low Duration
CLOCK to Control Setup Time
CLOCK to Control Hold Time
LOAD Period
LOAD High Duration
1
LOAD High to TC0–TC3 Setup Time
LOAD High to TC0–TC3 Hold Time
WR
Falling to
CS
Low Setup Time
WR
Falling to
CS
Low Hold Time
Minimum
WR
Low Duration
Minimum
WR
High Duration
WR
to D0–D15 Setup Time
WR
to D0–D15 Hold Time
SCLK Period
SCLK High Duration
SCLK Low Duration
SCLK Rising to SDATA Setup Time
SCLK Rising to SDATA Hold Time
NOTE
1
May be reduced to 1t
1
if LOAD is synchronized to CLOCK and Setup (t
4
) and Hold (t
5
) Times for LOAD to CLOCK are observed.
t
1
t
2
CLOCK
CS
t
10
t
11
t
3
t
4
FSEL, LOAD,
TC3–TC0
VALID
VALID
WR
t
12
t
14
D0–D15
t
13
t
15
t
5
VALID DATA
Figure 1. Clock Synchronization Timing
Figure 3. Parallel Port Timing
t
16
t
6
t
7
LOAD
SCLK
t
17
t
20
t
18
t
8
TC0–TC3
VALID
t
9
SDATA
t
19
DB31
DB0
Figure 2. Register Transfer Timing
Figure 4. Serial Port Timing
REV. B
–3–
AD [ ANALOG DEVICES ]
