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AD7008JP50 参数 Datasheet PDF下载

AD7008JP50图片预览
型号: AD7008JP50
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS DDS调制器 [CMOS DDS Modulator]
分类和应用: 数据分配系统
文件页数/大小: 16 页 / 507 K
品牌: ADI [ ADI ]
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AD7008  
{This section converts the twos complement au-  
dio into offset binary scaled formodulating  
the AD7008. If twos complement is used, the  
modulation scheme will instead bedouble side-  
band, suppressed carrier.}  
cillator application is with the AD607 Monoceiver(tm). This  
unique two chip combination provides a complete receiver sub-  
system with digital frequency control, RSSI and demodulated  
outputs for AM, FM and complex I/Q (SSB or QAM). (See  
Figure 13.)  
r5 = 0x80000000;  
r6 = r6 xor r5;  
r6 = lshift r6 by -1;  
r6 = r6 xor r5;  
Direct Digital Modulator  
In addition to the basic DDS function provided by the AD7008,  
the device also offers several modulation capabilities useful in a  
wide variety of application. The simplest modulation scheme is  
frequency shift keying or FSK. In this application, each of the  
two frequency registers is loaded with a different value, one rep-  
resenting the space frequency and the other the mark frequency.  
The digital data stream is fed to the FSELECT pin causing  
the AD7008 to modulate the carrier frequency between the two  
values.  
r4 = lshift r6 by -6;  
{Load parallel assembly register with modula-  
tion data. Q portion set to midscale, I  
portion with scaled data}  
r5 = 0x00000004;  
dm(dds_para) = r5;  
dm(dds_para) = r4;  
F SELECT  
{Transfer parallel assembly register to IQMOD  
register}  
1
1
CLOCK  
0
0
0
32  
32  
FREQ 0  
REG  
32  
r4 = 0xb0000000;  
dm(dds_cont) = r4;  
rti;  
32  
MUX  
FREQ 1  
REG  
PHASE  
ACCUMULATOR  
Many applications require precise control of the output ampli-  
tude, such as in local oscillators, signal generators and modula-  
tors. There are several methods to control signal amplitude.  
The most direct is to program the amplitude using the IQMOD  
register on the AD7008. Other methods include selecting the  
load resistor value or changing the value of RSET. Another op-  
tion is to place a voltage out DAC on the ground side of RSET as  
in Figure 16. This allows easy control of the output amplitude  
without affecting other functions of the AD7008. Any combina-  
tion of these techniques may be used as long as the full-scale  
voltage developed across the load does not exceed 1 volt.  
AD7008  
Figure 14. FSK Modulator  
The AD7008 has three registers that can be used for modula-  
tion. Besides the example of frequency modulation shown  
above, the frequency registers can be updated dynamically as  
can the phase register and the IQMOD register. These can be  
modulated at rates up to 16.5 MHz. The example shown below  
along with code fragment shows how to implement the AD7008  
in an amplitude modulation scheme. Other modulation  
schemes can be implemented in a similar fashion.  
U3  
AD7008  
C1  
19  
20  
21  
22  
23  
24  
25  
26  
8
6
5
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
+5V  
+5V  
DMD24  
DMD25  
DMD26  
DMD27  
DMD28  
DMD29  
DMD30  
DMD31  
DMD32  
DMD33  
DMD34  
DMD35  
DMD36  
DMD37  
DMD38  
DMD39  
V
DMDXX–DATA BITS  
DMAXX–ADDRESS BITS  
REF  
DSP:  
SCALE  
ANALOG  
INPUT TO  
FULL  
0.1µF  
C2  
I MOD  
10  
COMP  
0.1µF  
ADC  
R4  
2
1
SCALE  
49.9  
10  
IOUT  
10  
10  
SIN  
IOUT  
10-BIT DAC  
IOUT  
R3  
49.9  
D8  
D9  
IOUT  
9
U1  
74HC138  
6
10  
10  
11  
12  
13  
14  
15  
16  
27  
32  
33  
34  
35  
36  
41  
42  
31  
30  
38  
37  
SIN/COS  
ROM  
D10  
D11  
D12  
D13  
D14  
D15  
WR  
CS  
TC0  
TC1  
R5  
4
+5V  
DMS1  
DMWR  
7
9
G1  
10  
FSADJUST  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
4
5
G2A  
G2B  
COS  
10  
390  
10  
11  
12  
13  
14  
15  
10  
Q MOD  
V
3
AA  
+5V  
17  
28  
39  
V
DD  
3
2
1
0
+5V  
+5V  
+5V  
DMS3  
DMD36  
DMD37  
DMD38  
DMD39  
DMA02  
DMA01  
DMA00  
C
B
A
AD7008  
V
DD  
V
DD  
TC2  
TC3  
44  
7
18  
29  
43  
Figure 15. Amplitude Modulation  
AGND  
DGND  
DGND  
DGND  
DGND  
LOAD  
SCLK  
SDATA  
FSELECT  
CLK  
+5V  
U2  
50MHz  
{__________IRQ3 Interrupt Vector__________}  
14  
{in_audio is a port used to sample the audio  
signal. This signal is assumed to be twos  
complement. This interrupt should be serviced  
at an audio sample rate. This routine assumes  
that the AD7008 has been set up with the Ampli-  
tude Modulation Enabled.}  
V
CC  
RESET  
SLEEP  
RESET  
40  
TEST  
8
OUT  
EE  
VOLTAGE OUT DAC,  
i.e., AD7245A  
0 TO +1 VOLTS  
V
7
Ifs =  
6233 x (V  
–V  
)
K1115  
REF  
DAC  
R
SET  
irq3_asserted:  
{Get audio sample}  
r6=dm(in_audio);  
Figure 16. External Gain Adjustment  
REV. B  
–11–  
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