AD7008
PIN DESCRIPTION
Mnemonic
Function
Positive power supply for the analog section. A 0.1
µF
decoupling capacitor should be connected between V
AA
and
AGND. This is +5 V
±
5%.
Analog Ground.
Positive power supply for the digital section. A 0.1
µF
decoupling capacitor should be connected between V
DD
and DGND. This is +5 V
±
5%. Both V
AA
and V
DD
should be externally tied together.
Digital Ground; both AGND and DGND should be externally tied together.
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
IOUT
should be either tied directly to AGND or through an external load resistor to AGND.
Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
(mA) =
POWER SUPPLY
V
AA
AGND
V
DD
DGND
IOUT,
IOUT
FS ADJUST
ANALOG SIGNAL AND REFERENCE
6233
×V
REF
R
SET
V
REF
=
1.27
V nominal R
SET
= 390
Ω
typical
V
REF
Voltage Reference Input. A 0.1
µF
decoupling ceramic capacitor should be connected between V
REF
and V
AA
.
There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See
specifications for maximum range.
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1
µF
decoupling ceramic
capacitor should be connected between COMP and V
AA
.
Digital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the fre-
quency of this clock. The output frequency accuracy and phase noise is determined by this clock.
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III.
Register load, active high digital Input. This pin, in conjunction with TC3–TC0, control loading of internal regis-
ters from either the parallel or serial assembly registers. The load pin must be high at least 1t
1
. See Table II.
Transfer Control address bus, digital inputs. This address determines the source and destination registers that are
used during a transfer. The source register can either be the parallel assembly register or the serial assembly regis-
ter. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG,
PHASE REG or IQMOD REG. TC3–TC0 should be valid prior to LOAD rising and should not change until
LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II.
Chip Select, active low digital input. This input in conjunction with
WR
is used when writing to the parallel
assembly register.
Write, active low digital input. This input in conjunction with
CS
is used when writing to the parallel assembly
register.
Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports.
Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the
databus is configured for 8-bit operation, D8–D15 should be tied to DGND.
Serial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assem-
bly register.
Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first.
Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Inter-
nal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the
COMMAND REG to put the AD7008 into a low power sleep mode.
Register Reset, active high digital input. RESET clears the COMMAND REG and all the modulation registers to
zero.
Test Mode. This is used for factory test only and should be left as a No Connect.
–5–
COMP
DIGITAL INTERFACE AND CONTROL
CLOCK
FSELECT
LOAD
TC3–TC0
CS
WR
D7–D0
D15–D8
SCLK
SDATA
SLEEP
RESET
TEST
REV. B
AD [ ANALOG DEVICES ]
