AD7008
Parallel Configuration
sleep mode, amplitude control and synchronization logic. At
reset, the chip defaults to 8-bit bus, no amplitude control and
logic synchronized. The code fragment below indicates how
the initialization code for the AD7008 might look using the
ADSP-21020.
The AD7008 functions fully in the parallel mode. There are
two parallel modes of operation. Both are similar but are tai-
lored for different bus widths, 8 and 16 bits. All modes of op-
eration can be controlled by the parallel interface.
On power up and reset, the chip must be configured by instruc-
ting the command register how to operate. The command reg-
ister may be used to set the device up for 8- or 16-bit mode,
{dds_para is a port define to decode for
the parallel assembly register write pulse.
dds_cont is a port defined to decode for
the TC control Load pin. The Command reg-
ister must first be loaded with configura-
tion information. In this example, the chip
is set up for 16 bits data. See Table III
for details.}
U3
AD7008
C1
19
20
21
22
23
24
25
26
8
6
5
+5V
+5V
D0
D1
D2
D3
D4
D5
D6
D7
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
V
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
REF
0.1µF
C2
COMP
0.1µF
R4
2
1
r4 = 0x00010000; {16 bits, Normal Op., AM
disabled, Synchronizer
enabled}
dm(dds_para)=r4; {write data to parallel
assembly register}
r4 = 0x00000000;
dm(dds_cont)=r5; {No data written, data is
just transferred from
49.9
IOUT
R3
49.9
D8
D9
9
IOUT
U1
74HC138
6
10
11
12
13
14
15
D10
D11
D12
D13
D14
D15
WR
CS
TC0
TC1
R5
4
+5V
DMS1
DMWR
7
9
G1
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
4
5
FSADJUST
G2A
G2B
390
10
11
12
13
14
15
3
16
V
AA
+5V
17
28
39
3
2
1
27
32
33
34
35
36
41
42
31
30
38
37
V
V
V
DD
DD
+5V
+5V
+5V
DMA02
DMA01
DMA00
C
B
A
GND
DMD36
DMD37
DMD38
DMD39
parallel assembly
register to the command
register}
DD
TC2
TC3
44
7
18
29
43
AGND
DGND
DGND
DGND
DGND
LOAD
SCLK
SDATA
FSELECT
CLK
+5V
U2
50MHz
r4 = 0x051E0000; {1 MHz=051EB852, load high
word first}
dm(dds_para)=r4;
r4 = 0xB8520000; {Now load low word}
dm(dds_para)=r4;
r4 = 0x80000000; {Transfer data from the
parallel assembly
14
V
CC
RESET
SLEEP
RESET
40
TEST
8
OUT
EE
V
7
K1115
register to Freq0}
dm(dds_cont)=r4;
Figure 12. Parallel Interface to a 16- or 32-Bit DSP or
Microprocessor
Local Oscillator
The AD7008 is well suited for applications such as local oscilla-
tors used in super-heterodyne receivers. Although the AD7008
can be used in a variety of receiver designs, one simple local os-
AD7008
10 BITS
RSET
390Ω
FILTER
5Ω
5Ω
0.1µF
–16dBm
AM OUTPUT
10Ω
VMID
0°
RF
INPUT
(ANTENNA)
BANDPASS
FILTER
PLL INPUT
OPTIONAL
BPF
OR LPF
PLL
330Ω
330Ω
90°
10Ω
FM OUTPUT
100
nF
100
nF
4.7
µF
AGC
DETECTOR
MIDPOINT
BIAS
GENERATOR
AGC VOLTAGE
RECEIVED
SIGNAL
STRENGTH
INDICATOR
BIAS
CIRCUIT
PTAT
VOLTAGE
AD607
Figure 13. AD7008 and AD607 Receiver Circuit
–10–
REV. B
ADI [ ADI ]
