AD6620
Mode = 1
mode the DTACK signal goes low when data is available during
a read or when data has been latched during a write. The DTACK
signal stays low until the DS signal is released.
If the MODE input is held high the interface is in Mode 1. In
Mode 1 the RD signal becomes the data strobe (DS) and the
WR signal becomes a read/write (R/W) select signal. In this
tDD
tHC
N+3
1
N
N+4
N+1
N+2
N
CLK
2
tSC
R/W
2
DS
tSC
tHC
3
CS
tZD
tZR
DATA VALID
D[7:0]
A[2:0]
tSAM
tHA
ADDRESS VALID
tDTACK
tDTACK
DTACK
NOTES:
1
DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2
THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.
Figure 45. Mode 1 Read (MODE = VDD)
tSC
tHC
1
CLK
N
N+3
N+1
N+2
N*
2
R/W
2
DS
tHC
tSC
3
CS
tSAM
tHM
D[7:0]
A[2:0]
DATA VALID
tSAM
tHA
ADDRESS VALID
tDTACK
DTACK
tDTACK
NOTES:
1
2
3
ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE DTACK HIGH.
*THE NEXT WRITE MAY BE INITIATED ON CLK, N*
Figure 46. Mode 1 Write (MODE = VDD)
–34–
REV. A
ADI [ ADI ]
