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AD6620ASZ 参数 Datasheet PDF下载

AD6620ASZ图片预览
型号: AD6620ASZ
PDF下载: 下载PDF文件 查看货源
内容描述: 67 MSPS数字接收信号处理器 [67 MSPS Digital Receive Signal Processor]
分类和应用:
文件页数/大小: 44 页 / 374 K
品牌: ADI [ ADI ]
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AD6620  
Read Pseudocode  
int read_micro(ext_address);  
Auto Increment Feature  
To increase throughput, an auto increment feature is provided.  
This feature is controlled by Bits 6 and 7 of the AMR. If these  
bits are set to 00, the address remains the same after an internal  
access. If set to 01, the address is incremented after a read access  
has been performed. If set to 10, the address is incremented  
after a write access is performed. If set to 11, the address is incre-  
mented after each access, read or write. This allows the AD6620  
to be initialized in a much shorter time since the access to the  
LAR and AMR must occur only once to initialize or read-back  
the entire device.  
main();  
{
/* This code shows the reading of the NCO frequency register  
using the read_micro function as defined above. The variable  
address is the External Address A[2..0] and data is the value to  
be placed in the external interface register. The NCO register is  
located at Internal Address = 0x303.  
*/  
// holding registers for NCO byte wide access data  
int d3, d2, d1, d0;  
MICROPORT CONTROL  
// NCO frequency word (32-bits wide)  
External reads and writes are accomplished in one of two modes  
via the Microprocessor Port. The CS, RD (DS), RDY (DTACK),  
WR (R/W) and MODE pins are used to control the access. The  
specific function of these pins depends on whether the access is  
MODE 0 or MODE 1. The Mode 1 signal names are those  
listed on the pinout. The access mode is controlled by the  
MODE input as described in the following sections.  
// write AMR  
write_micro(7, 0x03 );  
// write LAR  
write_micro(6, 0x03);  
/* read D[7:0] from DR0, All data is moved from the Internal  
Registers to the interface registers on this access. Reading  
should be initiated with a read from DR0. Therefore, DR1,  
DR2 and DR3 can be read after DR0 */  
Table XII. Microprocessor Control Signals  
MODE 0  
MODE 1  
d0 = read_micro(0) & 0xFF;  
A[2:0] (Address Lines)  
D[7:0] (Data Lines)  
CS (Chip Select)  
A[2:0] (Address Lines)  
D[7:0] (Data Lines)  
CS (Chip Select)  
// read D[15:8] from DR1  
d1 = read_micro(1) & 0xFF;  
RD (Read Strobe)  
DS (Data Strobe)  
// read D[23:16] from DR2  
d2 = read_micro(2) & 0xFF;  
WR (Write Strobe)  
RDY (Ready Signal)  
MODE (Mode Select)  
R/W (Read/Write Select)  
DTACK (Data Acknowledge)  
MODE (Mode Select)  
// read D[31:24] from DR3  
d3 = read_micro(3) & 0xFF;  
The Microport is synchronous with the master clock (CLK) of  
the AD6620, but the interface is not required to be. If the speed  
of the interface is significantly slower than CLK, synchronicity  
should not be an issue. If the interface is relatively fast com-  
pared to CLK, the user may need to synchronize the Microport  
to CLK or add wait states to the controlling processor. The  
timing diagrams show the relationship of the control signals to  
clock and the user should use these as a guide to implement a  
Microport interface.  
// DR4 is not needed because NCO_FREQ is only 32-bits  
// Assemble 32-bit NCO_FREQ word from the 4 byte  
components  
NCO_FREQ = d0 + (d1 << 8) + (d2 << 16) + (d3 << 24);  
} // end of main  
REV. A  
–32–  
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