AD6620
Mode = 0
is accessing the chip, the RDY line goes low at the start of
the access. When the internal cycle is complete the RDY line
is released.
If MODE is low during the access, the interface is in Mode 0.
In Mode 0 the CS, RD and the WR lines control the access
type. While an access is being performed, or if the serial port
tDD
tHC
1
CLK
N
N+1
N+2
N+3
N+4
N
2
WR
tSC
2
RD
tHC
3
CS
tZD
tZR
DATA VALID
D[7:0]
A[2:0]
tHA
tSAM
ADDRESS VALID
tRDY
tRDY
1
RDY
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2
3
THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.
Figure 43. Mode 0 Read (MODE = GND)
tHC
tSC
1
CLK
N
N+1
N+2
N+3
N*
2
WR
2
RD
tSC
tHC
3
CS
tSAM
tHM
DATA VALID
D[7:0]
A[2:0]
RDY
tHA
ADDRESS VALID
tSAM
tRDYH
tRDYL
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
RISING EDGE OF CLK "N+2".
2
3
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
*THE NEXT WRITE MAY BE INITIATED ON CLK, N.
Figure 44. Mode 0 Write (MODE = GND)
–33–
REV. A
ADI [ ADI ]
