AD6620
ACCESS PROTOCOLS
Write Pseudocode
The AD6620 external accesses may be performed through either
the Microprocessor Port or the Serial Port. The Microport and
the serial port both use a three-bit address and eight-bit data to
access these registers. The three-bit address provides access to
seven register locations (External Interface Registers). These
register locations are used to access the internal address space of
the AD6620 shown in the Control Register section. The seven
registers are the LAR (Low Address Register), the AMR (Address
Mode Register), and the five data registers (DR4–DR0).
void write_micro(ext_address, int data);
main();
{
/* This code shows the programming of the NCO frequency
register using the write_micro function as defined above. The
variable address is the External Address A[2:0] and data is the
value to be placed in the external interface register. The NCO
register is located at Internal Address = 0x303
*/
// holding registers for NCO byte wide access data
int d3, d2, d1, d0;
Table XI. External Interface Registers
A[2:0]
Name
Comment
// NCO frequency word (32-bits wide)
NCO_FREQ = 0xCBEFEFFF;
000
001
010
011
100
101
110
111
Data Register 0 (DR0)
Data Register 1 (DR1)
Data Register 2 (DR2)
Data Register 3 (DR3)
Data Register 4 (DR4)
Reserved
D[7:0]
D[15:8]
D[23:16]
D[31:24]
D[35:32]
Reserved
A[7:0]
// write AMR
write_micro(7, 0x03);
// write LAR
write_micro(6, 0x03);
Low Address Register (LAR)
Address Mode Register (AMR) 1-0: A[9:8]
// DR4 is not needed because NCO_FREQ is only 32-bits, not
36
// write DR3 with high byte of 32 bit word (D[31:24]
d3 = (NCO_FREQ & 0xFF000000) >> 24;
write_micro(3, d3);
5-2: Reserved
6: Read Increment
7: Write Increment
The internal address space is accessed using a 10-bit internal
address. Many of these address locations are more than a byte
wide and require multiple accesses to the seven External Inter-
face Registers, which are each only 8 bits wide (only 4 bits of
DR4 are used). Accesses to these registers are accomplished
using the 3-bit address and 8-bit data lines the manner described
below. The source of these values depends on the control port
method used.
// write DR2 with high byte of 32 bit word (D[23:16]
d2 = (NCO_FREQ & 0xFF0000) >> 16;
write_micro(2, d2);
// write DR1 with D[15:8]
d1 = (NCO_FREQ & 0xFF00) >> 8;
write_micro(1, d1);
// write DR0 with D[7:0]
// Writing to DR0 causes all data to be transferred to the
internal address.
//Therefore, DR1, DR2 and DR3 should already be written
d0 = NCO_FREQ & 0xFF;
write_micro(0, d0);
All internal accesses are accomplished by first writing the inter-
nal address of the register or memory location to be accessed.
The lower eight address bits are written to the LAR register
and the upper two address bits to the LSBs of the AMR. This
defines the internal address of the location to be accessed as
shown in the memory map shown in the Control Registers and
On-Chip RAM section.
} // end of main
Internal Read Access
Internal Write Access
A read is performed by first writing the LAR and AMR as with a
write. The data registers (DR4–DR0) are then read in the reverse
order that they were written. First, the least significant byte of
the data (D[7:0]) is read from DR0. On this transaction the
high bytes of the data are moved from the internal address
pointed to by the LAR and AMR into the remaining data regis-
ters (DR4–DR1). This data can then be read from the data
registers using the appropriate 3-bit addresses. The number of
data registers used depends solely on the amount of data to be
read or written. Any unused bit in a data register should be
masked out for a read.
Up to 36 bits of data (as needed) can be written by the process
described below. Any high order bytes that are needed are writ-
ten to the corresponding data registers defined in the external
3-bit address space. The least significant byte is then written to
DR0 at address (000). When a write to DR0 is detected, the
internal microprocessor port state machine then moves the data
in DR4–DR0 to the internal address pointed to by the address
in the LAR and AMR.
REV. A
–31–
ADI [ ADI ]
