AD5382
HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. Reset is a negative edge-
sensitive input. The default corresponds to m at full scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT 0 to VOUT 31 to 0 V. This sequence takes 270 µs max.
The falling edge of RESET initiates the reset process; BUSY goes
low for the duration, returning high when RESET is complete.
While BUSY is low, all interfaces are disabled and all LDAC
pulses are ignored. When BUSY returns high, the part resumes
normal operation and the status of the RESET pin is ignored
until the next falling edge is detected.
FIFO OPERATION IN PARALLEL MODE
The AD5382 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO Enable (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DVDD, the internal FIFO is enabled, allowing the
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO_EN pin is
sampled on power-up, and after a CLEAR or RESET, to
determine if the FIFO is enabled. In either serial or I
2
C interface
modes, FIFO_EN should be tied low. Up to 128 successive
instructions can be written to the FIFO at maximum speed in
parallel mode. When the FIFO is full, any further writes to the
device are ignored. Figure 29 shows a comparison between
FIFO mode and non-FIFO mode in terms of channel update
time. Figure 29 also outlines digital loading time.
25
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low clears the contents of the DAC
registers to the data contained in the user configurable CLR
register and sets VOUT 0 to VOUT 31 accordingly. This func-
tion can be used in system calibration to load zero scale and full
scale to all channels. The execution time for a CLR is 35 µs.
20
WITHOUT FIFO
(CHANNEL UPDATE TIME)
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the
AD5382. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
of x2, the BUSY output goes low. While BUSY is low, the user
can continue writing new data to the x1, m, or c registers, but no
DAC output updates can take place. The DAC outputs are
updated by taking the LDAC input low. If LDAC goes low while
BUSY is active, the LDAC event is stored and the DAC outputs
update immediately after BUSY goes high. The user may hold
the LDAC input permanently low, in which case the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled and any events on LDAC are ignored. The AD5382
contains an extra feature whereby a DAC register is not updated
unless its x2 register has been written to since the last time
LDAC was brought low. Normally, when LDAC is brought low,
the DAC registers are filled with the contents of the x2 registers.
However, the AD5382 will only update the DAC register if the
x2 data has changed, thereby removing unnecessary digital
crosstalk.
TIME (µs)
15
10
WITH FIFO
(CHANNEL UPDATE TIME)
5
WITH FIFO
(DIGITAL LOADING TIME)
0
1
4
7
10
13 16 19 22 25 28
NUMBER OF WRITES
31
34
37
40
03731-0-018
Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)
POWER-ON RESET
The AD5382 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The
BUSY pin goes low during the power-on reset sequencing,
preventing data writes to the device.
POWER-DOWN
The AD5382 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 µA max and digital power consumption to
20 µA max. In power-down mode, the output amplifier can be
configured as a high impedance output or provide a 100 kΩ
load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier will elapse before the outputs settle
to their correct values.
Rev. 0 | Page 25 of 40
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