Data Sheet
gain in 6 dB steps.
Table 16.
SDI
0xC1XX
SDO
0xXXXX
Action
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
AD5232
During reliability qualification, Flash/EE memory is cycled
from 0x00 to 0xFF until a first fail is recorded, signifying the
endurance limit of the on-chip Flash/EE memory.
As indicated in the Specifications section, the
Flash/EE
memory endurance qualification has been carried out in accor-
dance with JEDEC Std. 22, Method A117 over the industrial
temperature range of −40°C to +85°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the
has been
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature of
T
J
= 55°C. As part of this qualification procedure, the Flash/EE
memory is cycled to its specified endurance limit, as described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data for
its full specified retention lifetime every time the Flash/EE
memory is repro-grammed. It should also be noted that
retention lifetime, based on an activation energy of 0.6 eV,
derates with T
J
, as shown in Figure 44.
300
0xC1XX
0xXXXX
Table 17.
SDI
0x3280
0x3340
SDO
0xXXXX
0xXXXX
Action
Stores 0x80 data in spare EEMEM location,
USER1.
Stores 0x40 data in spare EEMEM location,
USER2.
locations.
Table 18.
SDI
0x94XX
0x00XX
SDO
0xXXXX
0xXX80
Action
Prepares data read from USER3 location.
(USER3 is already loaded with 0x80.)
Instruction 0 (NOP) sends 16-bit word out
of SDO where the last eight bits contain
the contents of USER3 location. The NOP
command ensures that the device returns
to the idle power dissipation state.
250
RETENTION (Years)
200
150
ADI TYPICAL PERFORMANCE
AT T
J
= 55°C
EQUIPMENT CUSTOMER START-UP SEQUENCE
FOR A PCB CALIBRATED UNIT WITH PROTECTED
SETTINGS
1.
2.
3.
For the PCB setting, tie WP to GND to prevent changes in
the PCB wiper set position.
Set power V
DD
and V
SS
with respect to GND.
As an optional step, strobe the PR pin to ensure full power-
on preset of the wiper register with EEMEM contents in
unpredictable supply sequencing environments.
100
50
50
60
70
80
90
100
110
T
J
JUNCTION TEMPERATURE (°C)
Figure 44. Flash/EE Memory Data Retention
EVALUATION BOARD
Analog Devices, Inc., offers a user-friendly
evaluation kit that can be controlled by a personal computer
through a printer port. The driving program is self-contained;
no programming languages or skills are needed.
FLASH/EEMEM RELIABILITY
The Flash/EE memory array on the
is fully qualified
for two key Flash/EE memory characteristics: namely, Flash/EE
memory cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as follows:
1.
2.
3.
4.
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
Rev. C | Page 21 of 24
02618-044
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40
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