AD14060/AD14060L
18
16
14
12
10
8
AD 14060/AD 14060L ASSEMBLY
RECO MMEND ATIO NS
SO CKET INFO RMATIO N
Standard sockets and carriers are available for the AD14060/
AD14060L, if needed. Socket part number IC53-3084-262 and
carrier part number ICC-308-1 are available from Yamaichi
Electronics.
Y = 0.0796X + 1.17
RISE TIME
Tr im and For m
6
Y = 0.0467X + 0.55
T he AD14060/AD14060L will be shipped as shown on the final
page of the data sheet with untrimmed and unformed leads and
with the nonconductive tie bar in place. This avoids disturbance of
lead spacing and coplanarity prior to assembly. Optimally, the
leads should be trimmed, formed and solder-dipped just prior to
placement on the board.
4
FALL TIME
2
0
0
20
40
60
80 100 120 140 160 180 200
LOAD CAPACITANCE – pF
T rim/Form can be accomplished with a Universal T rim/Form,
Customer-Designed T rim/Form, or with the Analog Devices’
Developed T ooling described below.
Figure 33. Typical Output Rise Tim e (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V)
9
8
7
A trim/form tool specific to the AD14060/AD14060L has been
developed and is available for use by all parties at:
T intronics Industries
2122-A Metro Circle
Huntsville, AL 35801
205-650-0220
Y = 0.0391X + 0.36
6
5
4
Contact Person: T om Rice
RISE TIME
Y = 0.0305X + 0.24
T he package outline and dimensions resulting from this tool are
shown below. (Alternatively, the package can also be trimmed/
formed for cavity-down placement.)
3
2
1
0
FALL TIME
0
20
40
60
80 100 120 140 160 180 200
0.170
(4.318)
LOAD CAPACITANCE – pF
2.110 (53.59)
2.210 ±0.010 (56.134 ±0.254)
Figure 34. Typical Output Rise Tim e (0.8 V –2.0 V) vs.
Load Capacitance (VDD = 3.3 V)
5
4.5
4
3
2
1
Y = 0.0329X - 1.65
0.016 MIN
0° TO 8°
NOMINAL
0 TO 10 MILS
–0.7
–1
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
DETAIL "A"
Figure 35. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maxim um Case Tem perature) (VDD = 3.3 V)
REV. A
–39–
ADI [ ADI ]
