AD14060/AD14060L
JTAG Test Access P or t and Em ulation
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tT CK
T CK Period
tCK
5
6
8
18.5
4tCK
tCK
5
6
8
19
4tCK
ns
ns
ns
ns
ns
ns
tST AP
tHT AP
tSSYS
tHSYS
tT RST W
T DI, T MS Setup Before T CK High
T DI, T MS Hold After T CK High
System Inputs Setup Before T CK Low1
System Inputs Hold After T CK Low1
TRST Pulsewidth
Switching Characteristics:
tDT DO T DO Delay from T CK Low
tDSYS
System Outputs Delay After T CK Low 2
13
20
13
20
ns
ns
NOT ES
1System Inputs = DAT A47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, RPBA, IRQ2-0, FLAG2-0, DR0, DR1, T CLK0,
T CLK1, RCLK0, RCLK1, T FS0, T FS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT , LBOOT , BMS, CLKIN, RESET.
2System Outputs = DAT A47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG2-0, T IMEXP, DT 0,
DT 1, T CLK0, T CLK1, RCLK0, RCLK1, T FS0, T FS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 25. IEEE 11499.1 J TAG Test Access Port
REV. A
–36–
ADI [ ADI ]
